公开(公告)号：EP0146975A3

公开(公告)日：1988-04-20

申请号：EP84200830

申请日：1984-06-09

Applicant: Monolithic Memories, Inc.

Inventor： Chan, Albert ,  Fitzpatrick Mark ,  Bosnyak, Robert J. ,  Tsui, Cyrus ,  Goddard, Don

IPC: G11C29/00

CPC classification number: G11C29/025 ,  G11C17/14 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5006

Abstract: Test circuitry is included in a PROM memory for detecting shorts between bit lines and word lines and shorts or leaks in a memory cell. The circuitry enables a selected positive voltage to be applied across all memory cells in the memory so that the existence of leaky memory cells or shorts in the memory can be detected during testing. The test circuitry has no appreciable effect on the memory during normal operation of the memory.

公开(公告)号：EP0148510A3

公开(公告)日：1988-01-27

申请号：EP84200811

申请日：1984-06-08

Applicant: Monolithic Memories, Inc.

Inventor： Bosnyak, Robert J. ,  Chua, H.T. ,  Goddard, Donald ,  Wong, Sing

IPC: G11C17/00

CPC classification number: G11C17/18

Abstract: A unique programming means, suitable for use with programmable read-only memories (PROM), or other circuits utilizing programmable fuses, is provided which overcomes several distinct disadvantages of prior art programming means. The program means of this invention includes a Darlington pair of prgramming transistors which allows only a single programming transistor to be made large in order to carry the large programming current, and only a single high current drive signal need be applied to the single programming transistor, thereby minimizing power consumption and integrated circuit die area.

公开(公告)号：EP0181011A2

公开(公告)日：1986-05-14

申请号：EP85200848.1

申请日：1985-05-25

Applicant: Monolithic Memories, Inc.

Inventor： Bosnyak, Robert J.

IPC: G01R31/28 ,  H03K19/003

CPC classification number: G01R31/31701

Abstract: A circuit is provided which overrides the normal output signal of a sequential logic circuit, and provides an output signal indicative of the logical state of an internal node which is normally accessible via the output terminals of the sequential logic circuit. These output signals are provided to faciliate adequate testing of the sequential logic circuit in a minimum of time.

Abstract translation: 本发明提供一种电路，它覆盖了一个时序逻辑电路的正常输出信号，并提供关于指示的内部节点的所有逻辑状态，这是通过顺序逻辑电路的输出端子通常可的输出信号。 提供这些输出信号，旨在便利时序逻辑电路的足够的测试中的最小的时间。