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1.发明公开CONFIGURATION AND FABRICATION OF SEMICONDUCTOR STRUCTURE HAVING TWO LEVELS OF BURIED REGIONS 失效安排和方法埋区的半导体结构在两个层面上
公开(公告)号：EP0757847A1
公开(公告)日：1997-02-12
申请号：EP96903613.0
申请日：1996-01-17
发明人： FARRENKOPF, Douglas, R. , MERRILL, Richard, B. , SAHA, Samar , BREHMER, Kevin, E. , GADEPALLY, Kamesh , CACHARELIS, Philip, J.
CPC分类号： H01L21/761 , H01L21/822 , H01L21/8249 , H01L27/0203 , H01L27/0623 , H01L27/088 , Y10S148/085
摘要： Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricated from a semiconductor structure in which lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. An upper buried region of a selected conductivity type is situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. Another upper buried region of opposite conductivity type to the first-mentioned upper buried region is preferably situated along the upper semiconductor interface. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate. Complementary bipolar transistors can be integrated with complementary field-effect transistors in the structure.
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2.发明授权METHOD OF FABRICATION OF AN INTEGRATED CIRCUIT CHIP CONTAINING EEPROM AND CAPACITOR 失效过程执行EEPROM和一个电容含集成电路芯片
公开(公告)号：EP0725980B1
公开(公告)日：2001-12-05
申请号：EP95931647.2
申请日：1995-08-29
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115
CPC分类号： H01L27/11526 , H01L27/0611 , H01L27/0688 , H01L27/105 , H01L27/11529 , H01L27/11546 , H01L27/11551
摘要： An EEPROM cell is formed in an IC chip by using only three masking steps in addition to those required for the basic CMOS transistors in the chip. A first mask layer is used to define source/drain regions of select and memory transistors within the EEPROM cell; a second mask layer is used to define a tunneling region of the memory transistor;and a third mask layer is used to define a floating gate of the memory transistor and a gate of the select transistor. A control gate of the memory transistor is formed using the same mask that is used to define the gates of the CMOS transistors. The third and fourth mask layers may also be used to form the lower and upper electrodes, respectively, of a capacitor.
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3.发明公开METHOD OF FABRICATION OF AN INTEGRATED CIRCUIT CHIP CONTAINING EEPROM AND CAPACITOR 失效过程执行EEPROM和一个电容含集成电路芯片
公开(公告)号：EP0725980A1
公开(公告)日：1996-08-14
申请号：EP95931647.0
申请日：1995-08-29
CPC分类号： H01L27/11526 , H01L27/0611 , H01L27/0688 , H01L27/105 , H01L27/11529 , H01L27/11546 , H01L27/11551
摘要： An EEPROM cell is formed in an IC chip by using only three masking steps in addition to those required for the basic CMOS transistors in the chip. A first mask layer is used to define source/drain regions of select and memory transistors within the EEPROM cell; a second mask layer is used to define a tunneling region of the memory transistor;and a third mask layer is used to define a floating gate of the memory transistor and a gate of the select transistor. A control gate of the memory transistor is formed using the same mask that is used to define the gates of the CMOS transistors. The third and fourth mask layers may also be used to form the lower and upper electrodes, respectively, of a capacitor.
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