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    Semiconductor device having a thin film field-shaping structure
    3.
    发明公开
    Semiconductor device having a thin film field-shaping structure 审中-公开
    Halbleiteranordnung mit einemDünnschicht-Feldformungsstruktur

    公开(公告)号：EP1032046A1

    公开(公告)日：2000-08-30

    申请号：EP00101883.7

    申请日：2000-01-31

    申请人： FUJI ELECTRIC CO., LTD.

    发明人： Jimbo, Shinichi, c/o Fuji Electric Co., Ltd. ,  Saito, Jun, c/o Fuji Electric Co., Ltd. ,  Yamazaki,Tomoyuki, c/o Fuji Electric Co., Ltd.

    IPC分类号： H01L29/41 ,  H01L29/78 ,  H01L27/06

    CPC分类号： H01L29/7816 ,  H01L27/0611 ,  H01L29/402 ,  H01L29/404 ,  H01L29/7801 ,  H01L29/7821 ,  H01L29/7823 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device comprising: a semiconductor substrate (10), a dielectric film (18) formed on the semiconductor substrate, a first electrode (2) and a second electrode (3) separated from each other on the dielectric film; a spiral thin film layer (6) having both ends connected to the first electrode and the second electrode, respectively, the spiral thin film layer surrounding the first electrode, the thin film layer being formed on the dielectric layer, and a plurality (51) of p-n diodes (4,5) such as Zener diodes formed in series in the spiral thin film layer along a longitudinal direction of the spiral thin film layer to provide a uniform potential distribution in the spiral thin film layer.

    摘要翻译： 一种半导体器件，包括：半导体衬底（10），形成在所述半导体衬底上的电介质膜（18），在所述电介质膜上彼此分离的第一电极（2）和第二电极（3） 分别具有连接到第一电极和第二电极的螺旋薄膜层（6），围绕第一电极的螺旋形薄膜层，薄膜层形成在电介质层上，以及多个（51） 的pn二极管（4,5），例如齐纳二极管，沿着螺旋形薄膜层的纵向串联形成在螺旋形薄膜层中，以在螺旋形薄膜层中提供均匀的电势分布。

    INTEGRATED DRIVER PROCESS FLOW
    6.
    发明公开
    INTEGRATED DRIVER PROCESS FLOW 有权
    DRIVER一体化进程FLOW

    公开(公告)号：EP1509946A1

    公开(公告)日：2005-03-02

    申请号：EP03756181.8

    申请日：2003-05-14

    申请人： Silicon Light Machines Corporation

    发明人： HUNTER, James, A.

    IPC分类号： H01L21/00 ,  H01L21/82 ,  H01L21/302

    CPC分类号： G02B26/0808 ,  B81B2201/045 ,  B81B2207/015 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/016 ,  B81C2203/0735 ,  B81C2203/0778 ,  H01L27/0611

    摘要： An integrated device including one or more device drivers and a diffractive light modulator monolithically coupled to the one or more driver circuits. The one or more driver circuits are configured to process received control signals and to transmit the processed control signals to the diffractive light modulator. A method of fabricating the integrated device preferably comprises fabricating a front-end portion for each of a plurality of transistors, isolating the front-end portions of the plurality of transistors, fabricating a front-end portion of a diffractive light modulator, isolating the front-end portion of the diffractive light modulator, fabricating interconnects for the plurality of transistors, applying an open array mask and wet etch to access the diffractive light modulator, and fabricating a back-end portion of the diffractive light modulator, thereby monolithically coupling the diffractive light modulator and the plurality of transistors.

    Electronic semiconductor power device with integrated diode
    8.
    发明公开
    Electronic semiconductor power device with integrated diode 有权
    Elektronische Halbleiterleistungsanordnung mit integrierter Diode

    公开(公告)号：EP1022785A1

    公开(公告)日：2000-07-26

    申请号：EP99830023.0

    申请日：1999-01-25

    申请人： STMicroelectronics S.r.l.

    发明人： Fragapane, Leonardo

    IPC分类号： H01L29/739 ,  H01L29/10 ,  H01L27/06

    CPC分类号： H01L29/1095 ,  H01L27/0611 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00

    摘要： The device, an IGBT, is formed on a chip (9) of silicon consisting of a P type substrate (10) with an N type epitaxial layer (11) which contains a first P type region (13) and a termination structure. This structure comprises a first P type termination region (14) which surrounds the first region (13), a first electrode (18) in contact with the first termination region (14) and a second electrode (21) shaped in the form of a frame close to the edge of the chip and connected to a third electrode (17) in contact with the bottom of the chip. A fourth electrode made in one piece with the first electrode (18) is in contact with the first region (13). To produce an integrated diode with good electrical characteristics connected in reverse conduction between the power terminals of the IGBT, the termination structure also comprises a fifth electrode (30), in contact with the epitaxial layer (11) along a path parallel to the edge of the first termination region (14), connected to the second electrode (21), a second P type termination region (32) which surrounds the fifth electrode (30) and a sixth electrode (33), in contact with the second termination region (32), connected to the first electrode (18).

    摘要翻译： 器件IGBT是形成在由包含第一P型区域（13）和端接结构的N型外延层（11）的P型衬底（10）构成的硅芯片（9）上。 该结构包括围绕第一区域（13）的第一P型端接区域（14），与第一端接区域（14）接触的第一电极（18）和形成为第一区域 框架靠近芯片的边缘并且连接到与芯片的底部接触的第三电极（17）。 与第一电极（18）一体制成的第四电极与第一区域（13）接触。 为了产生具有良好的电特性的集成二极管，其在IGBT的功率端之间被反向导通，所述端接结构还包括与外延层（11）接触的第五电极（30），该第五电极沿平行于 连接到第二电极（21）的第一端接区域（14），围绕第五电极（30）的第二P型端接区域（32）和与第二端接区域接触的第六电极（33） 32），连接到第一电极（18）。

    Method of manufacturing metal-semiconductor field effect transistors
    9.
    发明公开
    Method of manufacturing metal-semiconductor field effect transistors 失效
    Feldeffekttransistoren enthaltendes Bauelement und dessen Herstellungsverfahren。

    公开(公告)号：EP0338251A1

    公开(公告)日：1989-10-25

    申请号：EP89104703.7

    申请日：1989-03-16

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Iwasaki, Hiroshi c/o Patent Division K.K. Toshiba

    IPC分类号： H01L27/06 ,  H01L21/82

    CPC分类号： H01L29/66878 ,  H01L21/8252 ,  H01L27/0611 ,  H01L29/1029

    摘要： A semiconductor device which comprises a semi-­insulating substrate (1) and a plurality of field effect transistors (FETs) formed on the semi-insulating sub­strate (1). An epitaxial layer (2)of one conductivity type is formed on the semi-insulating substrate by a crystal growth technique which is capable of controlling a film thickness at an atomic level. At least some of channel active layers of the FETs have different threshold voltages one another due to a difference in thickness of the epitaxial layer (2) and/or due to an additional ion implantation region selectively formed in the epitaxial layer (2). A manufacturing method of the semiconductor device is also disclosed, wherein a portion of the epitaxial layer (2) corresponding to the channel active layer of a FET is thickened by the repetition of an epitaxial growth, thinned by the etching of the epitaxial layer or ion implanted thereby obtaining a different threshold voltage from that of another FET.

    摘要翻译： 一种半导体器件，包括半绝缘衬底（1）和形成在半绝缘衬底（1）上的多个场效应晶体管（FET）。 通过能够以原子级控制膜厚度的晶体生长技术，在半绝缘基板上形成一种导电类型的外延层（2）。 由于外延层（2）的厚度差异和/或由于在外延层（2）中选择性地形成的另外的离子注入区域，FET的至少一些沟道有源层彼此具有不同的阈值电压。 还公开了半导体器件的制造方法，其中对应于FET的沟道有源层的外延层（2）的一部分通过外延生长的重复而增厚，通过蚀刻外延层或离子而变薄 植入，从而获得与另一FET的阈值电压不同的阈值电压。