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11 条记录 (耗时 0.015 秒)

    Phase-locked loop circuit
    2.
    发明公开
    Phase-locked loop circuit 失效
    Phasenregelkreisschaltung。

    公开(公告)号：EP0072751A2

    公开(公告)日：1983-02-23

    申请号：EP82401522.6

    申请日：1982-08-11

    申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION ,  FUJITSU LIMITED

    发明人： Iwata, Atsushi ,  Kaneko, Takao ,  Ito, Akihiko ,  Saito, Tadahiro ,  Fukui, Hirokazu

    IPC分类号： H03L7/08

    CPC分类号： H03L7/0895

    摘要： The phase-locked loop circuit provides a phase comparator which receives input signals through a first input terminal, a loop filter which receives a first output and a second output of the phase comparator, and a voltage-controlled oscillator which produces output signals of an oscillation frequency proportional to the first output and the second output of the loop filter, the signals corresponding to output signals produced by the voltage-controlled oscillator being supplied to a second input terminal of the phase comparator so that the phase of the signals supplied to the first input terminal of the phase comparator is compared with the phase of the signals supplied to the second input terminal. In the present invention, the loop filter comprise a first capacitor connected to the output terminal of the loop filter, a second capacitor and a third capacitor each having a terminal connected to the output terminal of the loop filter, a charging circuit for electrically charging the first, second, and third capacitors, the charging circuit being connected in parallel with the second capacitor, and a discharging circuit for discharging the first, second, and third capacitors, the discharging circuit being connected in parallel with the third capacitor.

    摘要翻译： 锁相环电路提供一个相位比较器，它通过第一输入端接收输入信号，一个接收相位比较器的第一输出和第二输出的环路滤波器，以及产生振荡输出信号的压控振荡器 频率与环路滤波器的第一输出和第二输出成比例，对应于由压控振荡器产生的输出信号的信号被提供给相位比较器的第二输入端，使得提供给第一 将相位比较器的输入端与提供给第二输入端的信号的相位进行比较。 在本发明中 环路滤波器包括连接到环路滤波器的输出端的第一电容器，第二电容器和第三电容器，每个电容器具有连接到环路滤波器的输出端子的端子;充电电路，用于对第一，第二和/ 第三电容器，充电电路与第二电容器并联连接;以及放电电路，用于对第一，第二和第三电容器进行放电，放电电路与第三电容器并联连接。

    Phase-locked loop circuit
    3.
    发明公开
    Phase-locked loop circuit 失效
    相位锁定环路

    公开(公告)号：EP0072751A3

    公开(公告)日：1983-08-24

    申请号：EP82401522

    申请日：1982-08-11

    申请人： Nippon Telegraph and Telephone Public Corporation ,  FUJITSU LIMITED

    发明人： Iwata, Atsushi ,  Kaneko, Takao ,  Ito, Akihiko ,  Saito, Tadahiro ,  Fukui, Hirokazu

    IPC分类号： H03L07/08

    CPC分类号： H03L7/0895

    摘要： The phase-locked loop circuit provides a phase comparator which receives input signals through a first input terminal, a loop filter which receives a first output and a second output of the phase comparator, and a voltage-controlled oscillator which produces output signals of an oscillation frequency proportional to the first output and the second output of the loop filter, the signals corresponding to output signals produced by the voltage-controlled oscillator being supplied to a second input terminal of the phase comparator so that the phase of the signals supplied to the first input terminal of the phase comparator is compared with the phase of the signals supplied to the second input terminal. In the present invention, the loop filter comprise a first capacitor connected to the output terminal of the loop filter, a second capacitor and a third capacitor each having a terminal connected to the output terminal of the loop filter, a charging circuit for electrically charging the first, second, and third capacitors, the charging circuit being connected in parallel with the second capacitor, and a discharging circuit for discharging the first, second, and third capacitors, the discharging circuit being connected in parallel with the third capacitor.

    Clock generator circuit
    5.
    发明公开
    Clock generator circuit 失效
    时钟电路。

    公开(公告)号：EP0053014A1

    公开(公告)日：1982-06-02

    申请号：EP81305484.8

    申请日：1981-11-20

    申请人： FUJITSU LIMITED

    发明人： Ito, Akihiko ,  Tanaka, Hisami ,  Takayama, Yoshihisa ,  Kato, Seiji

    IPC分类号： H03K5/15

    CPC分类号： H03K5/1515

    摘要： A clock generator circuit for generating two pairs of clock signals (φ 2 , φ 2 - φ 1 , φ 1 ) comprises a NAND circuit (51) and a NOR circuit (52) cross-coupled to each other and each having an input for receiving a reference clock signal (φ 0 ). A first inverter (53) is provided between the output of the NAND cicuit (51) and the other input of the NOR circuit (52), and a second inverter (54) is provided between the output of the NOR circuit (52) and the other input of the NAND circuit (51). A pair of clock signals ( φ 2 , φ 2 ) are generated from the NAND circuit (51) and the first inverter (53), while the other pair of clock signals (φ 1 , φ 1 ) are generated from the NOR circuit (52) and the second inverter (54). Unwanted overlap of such clock signals can thereby be avoided.

    Switched-capacitor filter
    9.
    发明公开
    Switched-capacitor filter 失效
    过滤器geschalteten Kondensatoren。

    公开(公告)号：EP0020131A1

    公开(公告)日：1980-12-10

    申请号：EP80301758.1

    申请日：1980-05-28

    申请人： FUJITSU LIMITED ,  Nippon Telegraph and Telephone Public Corporation

    发明人： Kato, Seiji ,  Ueno, Norio ,  Kakuishi, Mitsuo ,  Ito, Akihiko ,  Iwata, Atsushi

    IPC分类号： H03H19/00

    CPC分类号： H03H19/004

    摘要： The passive prefilter (61) is comprised only of a plurality of additional switched capacitors (62) which are added to a switched capacitor (63) common to a switched-capacitor filter (32). The switched capacitor (63) common to said switched-capacitor filter is driven by clock pulses at the sampling frequency of the filter. The prefilter samples and holds the input signal (VSin) at a rate equal to an even harmonic of the sampling frequency, combines all signals held over a sampling period, and provides the filter (32) with this summed signal (Vout). The prefilter reduces substantially any calias signals», that is input signals (VSin) of a frequency close to the sampling frequency or to an harmonic of the sampling frequency.

    摘要翻译： 无源前置滤波器（61）仅由添加到开关电容滤波器（32）公共的开关电容器（63）的多个附加开关电容器（62）组成。 所述开关电容滤波器共用的开关电容器（63）由滤波器的采样频率的时钟脉冲驱动。 预滤波器以等于采样频率的偶次谐波的速率采样并保持输入信号（VSin），合并在采样周期内保持的所有信号，并向滤波器（32）提供该求和信号（Vout）。 预滤器基本上减少了任何“别名信号”，即接近采样频率的频率或采样频率的谐波的输入信号（VSin）。