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10 条记录 (耗时 0.013 秒)

    Phase-locked loop circuit
    1.
    发明公开
    Phase-locked loop circuit 失效
    相位锁定环路

    公开(公告)号：EP0072751A3

    公开(公告)日：1983-08-24

    申请号：EP82401522

    申请日：1982-08-11

    申请人： Nippon Telegraph and Telephone Public Corporation ,  FUJITSU LIMITED

    发明人： Iwata, Atsushi ,  Kaneko, Takao ,  Ito, Akihiko ,  Saito, Tadahiro ,  Fukui, Hirokazu

    IPC分类号： H03L07/08

    CPC分类号： H03L7/0895

    摘要： The phase-locked loop circuit provides a phase comparator which receives input signals through a first input terminal, a loop filter which receives a first output and a second output of the phase comparator, and a voltage-controlled oscillator which produces output signals of an oscillation frequency proportional to the first output and the second output of the loop filter, the signals corresponding to output signals produced by the voltage-controlled oscillator being supplied to a second input terminal of the phase comparator so that the phase of the signals supplied to the first input terminal of the phase comparator is compared with the phase of the signals supplied to the second input terminal. In the present invention, the loop filter comprise a first capacitor connected to the output terminal of the loop filter, a second capacitor and a third capacitor each having a terminal connected to the output terminal of the loop filter, a charging circuit for electrically charging the first, second, and third capacitors, the charging circuit being connected in parallel with the second capacitor, and a discharging circuit for discharging the first, second, and third capacitors, the discharging circuit being connected in parallel with the third capacitor.

    Phase-locked loop circuit
    2.
    发明公开
    Phase-locked loop circuit 失效
    Phasenregelkreisschaltung。

    公开(公告)号：EP0072751A2

    公开(公告)日：1983-02-23

    申请号：EP82401522.6

    申请日：1982-08-11

    申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION ,  FUJITSU LIMITED

    发明人： Iwata, Atsushi ,  Kaneko, Takao ,  Ito, Akihiko ,  Saito, Tadahiro ,  Fukui, Hirokazu

    IPC分类号： H03L7/08

    CPC分类号： H03L7/0895

    摘要： The phase-locked loop circuit provides a phase comparator which receives input signals through a first input terminal, a loop filter which receives a first output and a second output of the phase comparator, and a voltage-controlled oscillator which produces output signals of an oscillation frequency proportional to the first output and the second output of the loop filter, the signals corresponding to output signals produced by the voltage-controlled oscillator being supplied to a second input terminal of the phase comparator so that the phase of the signals supplied to the first input terminal of the phase comparator is compared with the phase of the signals supplied to the second input terminal. In the present invention, the loop filter comprise a first capacitor connected to the output terminal of the loop filter, a second capacitor and a third capacitor each having a terminal connected to the output terminal of the loop filter, a charging circuit for electrically charging the first, second, and third capacitors, the charging circuit being connected in parallel with the second capacitor, and a discharging circuit for discharging the first, second, and third capacitors, the discharging circuit being connected in parallel with the third capacitor.

    摘要翻译： 锁相环电路提供一个相位比较器，它通过第一输入端接收输入信号，一个接收相位比较器的第一输出和第二输出的环路滤波器，以及产生振荡输出信号的压控振荡器 频率与环路滤波器的第一输出和第二输出成比例，对应于由压控振荡器产生的输出信号的信号被提供给相位比较器的第二输入端，使得提供给第一 将相位比较器的输入端与提供给第二输入端的信号的相位进行比较。 在本发明中 环路滤波器包括连接到环路滤波器的输出端的第一电容器，第二电容器和第三电容器，每个电容器具有连接到环路滤波器的输出端子的端子;充电电路，用于对第一，第二和/ 第三电容器，充电电路与第二电容器并联连接;以及放电电路，用于对第一，第二和第三电容器进行放电，放电电路与第三电容器并联连接。

    CMOS semiconductor device
    3.
    发明公开
    CMOS semiconductor device 失效
    CMOS-Halbleitervorrichtung。

    公开(公告)号：EP0023791A1

    公开(公告)日：1981-02-11

    申请号：EP80302470.2

    申请日：1980-07-21

    申请人： FUJITSU LIMITED

    发明人： Ito, Akihiko ,  Saito, Tadahiro

    IPC分类号： H01L27/08

    CPC分类号： H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device may include both analogue and digital CMOS elements formed on the same ship with each of the CMOS elements having a conventional source region (16), a drain region (15), and a diffusion region (14, 17) located adjacent to it. In this case, in the past the diffusion region (14, 17) and the source region (16) have always been connected together and to a power supply terminal by a common conductor (31). This has resulted in noise picked up by the diffusion region (14, 17) being transmitted directly to the source region (16). This defect is overcome by using separate conductors (31-1) and (31-2) which are physically independent of each other with one conductor (31-1) being connected between a power supply terminal (+Vss) and the source region (16), and the other conductor (31-2) being connected between the power supply terminal (+ Vss) and the diffusion region (14,17).

    摘要翻译： 半导体器件可以包括形成在同一艘船上的模拟和数字CMOS元件，其中每个CMOS元件具有常规源极区域（16），漏极区域（15）和位于邻近的扩散区域（14,17） 它。 在这种情况下，过去，扩散区域（14,17）和源极区域（16）总是通过公共导体（31）连接在一起而与电源端子连接。 这导致由扩散区域（14,17）直接传输到源极区域（16）的噪声。 通过使用在电源端子（+ VSS）和源极区域（+ VSS）之间连接一个导体（31-1）的物理上彼此独立的单独的导体（31-1）和（31-2）来克服该缺陷， 16），另一个导体（31-2）连接在电源端（+ VSS）和扩散区（14,17）之间。

    Semiconductor integrated circuit
    6.
    发明公开
    Semiconductor integrated circuit 失效
    Integrierte Halbleiterschaltung。

    公开(公告)号：EP0192456A2

    公开(公告)日：1986-08-27

    申请号：EP86301107.8

    申请日：1986-02-18

    申请人： FUJITSU LIMITED

    发明人： Saito, Tadahiro ,  Gotoh, Kunihiko

    IPC分类号： H04M1/24 ,  H04M1/50 ,  H04M1/31 ,  G01R31/28

    CPC分类号： H04M1/24 ,  H04M1/312 ,  H04M1/50

    摘要： In a semiconductor integrated circuit (10) comprising an internal circuit (9), an oscillating circuit (1) generating a basic clock signal for operating the internal circuit (9) when the internal circuit is operated in a usual mode, a pair of terminals (Toscin, Toscout) connected to the input side and output side of the oscillating circuit (1), respectively, an oscillator (8) being connected between the above pair of terminals (Toscin, Toscout) when the internal circuit (9) is , operated in a usual mode, a reset terminal (Treset) through which a reset signal for resetting the internal circuit is supplied from outside the integrated circuit (10) to the internal circuit, and a test circuit (3, 4, 5) for operating the internal circuit (9) in a test mode; the test circuit supplies a clock signal for testing from outside the integrated circuit to the internal circuit (9) through one of the above pair of terminals (Toscout) when signals of a predetermined level are supplied from outside of the chip to the test circuit through each of the other one of the above pair of terminals (Toscin) and the reset terminal (Treset).

    摘要翻译： 在包括内部电路（9）的半导体集成电路（10）中，当内部电路以常规模式操作时，产生用于操作内部电路（9）的基本时钟信号的振荡电路（1），一对端子 （Toscin，Toscout）分别连接到振荡电路（1）的输入侧和输出侧，当内部电路（9）被操作时，连接在上述一对端子（Toscin，Toscout）之间的振荡器（8） 在通常的模式中，复位端子（Treset）通过该复位端子（Treset）将用于复位内部电路的复位信号从集成电路（10）的外部提供给内部电路;以及测试电路（3,4,5） 内部电路（9）处于测试模式; 当从芯片的外部向测试电路提供预定电平的信号时，测试电路通过上述一对端子（Toscout）中的一个将集成电路外部的测试时钟信号提供给内部电路（9） 上述一对终端（Toscin）和复位终端（Treset）中的每一个。

    Semiconductor integrated circuit
    8.
    发明公开
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：EP0192456A3

    公开(公告)日：1989-04-05

    申请号：EP86301107.8

    申请日：1986-02-18

    申请人： FUJITSU LIMITED

    发明人： Saito, Tadahiro ,  Gotoh, Kunihiko

    IPC分类号： H04M1/24 ,  H04M1/50 ,  H04M1/31 ,  G01R31/28

    CPC分类号： H04M1/24 ,  H04M1/312 ,  H04M1/50

    摘要： In a semiconductor integrated circuit (10) comprising an internal circuit (9), an oscillating circuit (1) generating a basic clock signal for operating the internal circuit (9) when the internal circuit is operated in a usual mode, a pair of terminals (Toscin, Toscout) connected to the input side and output side of the oscillating circuit (1), respectively, an oscillator (8) being connected between the above pair of terminals (Toscin, Toscout) when the internal circuit (9) is , operated in a usual mode, a reset terminal (Treset) through which a reset signal for resetting the internal circuit is supplied from outside the integrated circuit (10) to the internal circuit, and a test circuit (3, 4, 5) for operating the internal circuit (9) in a test mode; the test circuit supplies a clock signal for testing from outside the integrated circuit to the internal circuit (9) through one of the above pair of terminals (Toscout) when signals of a predetermined level are supplied from outside of the chip to the test circuit through each of the other one of the above pair of terminals (Toscin) and the reset terminal (Treset).

    摘要翻译： 在包括内部电路（9）的半导体集成电路（10）中，当内部电路以通常模式工作时产生用于操作内部电路（9）的基本时钟信号的振荡电路（1），一对端子 （Toscin，Toscout），分别连接到振荡电路（1）的输入侧和输出侧;振荡器（8），当内部电路（9）接通时，连接在上述一对端子（Toscin，Toscout） 以正常模式操作;复位端子（Treset），通过该复位端子将用于复位内部电路的复位信号从集成电路（10）外部提供给内部电路;以及测试电路（3,4,5），用于操作 内部电路（9）处于测试模式; 当预定电平的信号从芯片的外部提供给测试电路时，测试电路通过上述一对端子（Toscout）中的一个将从集成电路外部测试的时钟信号提供给内部电路（9） 上述一对端子中的另一个（Toscin）和复位端子（Treset）中的每一个。