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    Two differential amplifier configuration
    1.
    发明公开
    Two differential amplifier configuration 审中-公开
    Zweifache差异Verstärkerkonfiguration

    公开(公告)号：EP2996244A1

    公开(公告)日：2016-03-16

    申请号：EP15153094.6

    申请日：2015-01-29

    申请人： ESS Technology, Inc.

    发明人： Mallinson, A. Martin

    IPC分类号： H03F1/34 ,  H03F3/45

    CPC分类号： H03F3/45076 ,  H03F1/0205 ,  H03F1/34 ,  H03F3/45475 ,  H03F3/45941 ,  H03F3/4595 ,  H03F2200/09 ,  H03F2203/45114 ,  H03F2203/45116 ,  H03F2203/45138 ,  H03F2203/45224 ,  H03F2203/45336 ,  H03F2203/45416 ,  H03F2203/45446 ,  H03F2203/45521 ,  H03F2203/45528 ,  H03F2203/45594

    摘要： An apparatus is disclosed for providing a common mode voltage to the inputs of a first differential amplifier (404, R3, R4) which outputs the difference between two signals. A second differential amplifier (406, R9, R10) receives the output of the first differential amplifier (404, R3, R4), and the output of the second differential amplifier (406, R9, R10) is fed back to the inputs of the first differential amplifier (404, R3, R4) as a common mode voltage. Since both inputs of the first differential amplifier (404, R3, R4) receive the fed back common mode voltage, the first differential amplifier (404, R3, R4) still outputs only the difference in the two signals, but the presence of the common mode voltage allows the first differential amplifier (404, R3, R4) to operate with lower noise if the voltage levels of the inputs to the first differential amplifier (404, R3, R4) vary. The second differential amplifier (406, R9, R10) may be of significantly lower quality and cost than the first differential amplifier (404, R3, R4), without affecting the performance of the first differential amplifier (404, R3, R4).

    摘要翻译： 公开了一种用于向输出两个信号之间的差的第一差分放大器（404，R3，R4）的输入端提供共模电压的装置。 第二差分放大器（406，R9，R10）接收第一差分放大器（404，R3，R4）的输出，第二差分放大器（406，R9，R10）的输出反馈到 第一差分放大器（404，R3，R4）作为共模电压。 由于第一差分放大器（404，R3，R4）的两个输入都接收反馈共模电压，所以第一差分放大器（404，R3，R4）仍然仅输出两个信号的差值， 如果第一差分放大器（404，R3，R4）的输入的电压电平变化，则模式电压允许第一差分放大器（404，R3，R4）以更低的噪声工作。 与第一差分放大器（404，R3，R4）相比，第二差分放大器（406，R9，R10）的质量和成本可以低得多，而不会影响第一差分放大器（404，R3，R4）的性能。

    Amplifier
    2.
    发明公开
    Amplifier 审中-公开
    放大器

    公开(公告)号：EP2317646A1

    公开(公告)日：2011-05-04

    申请号：EP09252522.9

    申请日：2009-10-30

    申请人： ST-Ericsson SA

    发明人： Teng, Robert Hwat Hian

    IPC分类号： H03F3/187 ,  H03F3/45

    CPC分类号： H03F3/45475 ,  H03F3/187 ,  H03F3/45179 ,  H03F3/45278 ,  H03F3/45645 ,  H03F3/45928 ,  H03F2200/03 ,  H03F2200/231 ,  H03F2200/234 ,  H03F2200/27 ,  H03F2200/375 ,  H03F2200/396 ,  H03F2200/411 ,  H03F2200/414 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/507 ,  H03F2200/78 ,  H03F2203/45101 ,  H03F2203/45116 ,  H03F2203/45138 ,  H03F2203/45206 ,  H03F2203/45212 ,  H03F2203/45222 ,  H03F2203/45224 ,  H03F2203/45356 ,  H03F2203/45536 ,  H03F2203/45561 ,  H03F2203/45588 ,  H03F2203/45616 ,  H03F2203/45641 ,  H03F2203/45728

    摘要： An amplifier 100 has an input 108 for receiving a signal to be amplified and an output 110 for outputting an amplified signal. The amplifier 100 comprises a main amplification stage 102, an auxiliary amplification stage 104 and a controller 106. The main amplification stage 102 comprises a main amplification circuit 200 and the auxiliary amplification stage 104 comprises an auxiliary amplification circuit 202. Each of the main amplification circuit 200 and the auxiliary amplification circuit 202 comprises a p-channel metal oxide semiconductor (PMOS) transistor T1, T3 and an n-channel metal oxide semiconductor (NMOS) transistor T2, T4. The PMOS and NMOS transistors T3, T4 of the auxiliary amplification circuit 202 are either identical to the PMOS and NMOS transistors T1, T2 of the main amplification circuit 200 or are scaled down copies of the PMOS and NMOS transistors T1, T2 of the main amplification circuit 200. The auxiliary amplification circuit 202 amplifies the input signal to generate a control signal and the controller 106 controls a function of the amplifier 100 based on the control signal.

    摘要翻译： 放大器100具有用于接收待放大信号的输入端108和用于输出放大信号的输出端110。 放大器100包括主放大级102，辅助放大级104和控制器106.主放大级102包括主放大电路200，辅助放大级104包括辅助放大电路202.每个主放大电路 200和辅助放大电路202包括p沟道金属氧化物半导体（PMOS）晶体管T1，T3和n沟道金属氧化物半导体（NMOS）晶体管T2，T4。 辅助放大电路202的PMOS和NMOS晶体管T3，T4或者与主放大电路200的PMOS和NMOS晶体管T1，T2相同，或者是主放大的PMOS和NMOS晶体管T1，T2的缩小副本 辅助放大电路202放大输入信号以生成控制信号，并且控制器106基于控制信号来控制放大器100的功能。

    Amplifier arrangement and method for signal amplification
    5.
    发明公开
    Amplifier arrangement and method for signal amplification 有权
    Verstärkungsanordnungund Verfahren zurSignalverstärkung

    公开(公告)号：EP2109214A1

    公开(公告)日：2009-10-14

    申请号：EP08007154.1

    申请日：2008-04-10

    申请人： Austriamicrosystems AG

    发明人： Sharma, Vivek

    IPC分类号： H03F1/02 ,  H03F1/08 ,  H03F3/45 ,  H03F3/72 ,  H03F3/00

    CPC分类号： H03F3/45475 ,  H03F1/0277 ,  H03F1/083 ,  H03F3/005 ,  H03F3/45179 ,  H03F3/72 ,  H03F2203/45112 ,  H03F2203/45224 ,  H03F2203/45288 ,  H03F2203/45292 ,  H03F2203/45318 ,  H03F2203/45352 ,  H03F2203/45396 ,  H03F2203/45626 ,  H03F2203/45726 ,  H03F2203/7236

    摘要： An amplifier arrangement comprises a signal input (Iin+, Iin- ) to receive a signal to be amplified, a signal output (Out) to provide an amplified signal, an amplifier stage (AS) coupled between the signal input (Iin+, Iin-) and the signal output (Out), a switchable dynamic biasing stage (DB) with an input coupled to the signal input (Iin+, Iin-), a switchable gain boosting stage (GB) with an input coupled to the signal input (Iin+, Iin-), and a switching device (SD) coupled to the amplifier stage (AS) such that either an output of the switchable dynamic biasing stage (DB) or an output of the switchable gain boosting stage (GB) are coupled to the amplifier stage (AS). In one embodiment, by enabling the switchable dynamic biasing stage (DB) in an initial large-signal phase of amplification and the switchable gain boosting stage (GB) in a latter small-signal phase of amplification by means of the switching device (SD), high gain and low current consumption are simultaneously realised. Furthermore, a method for signal amplification is provided.

    摘要翻译： 放大器装置包括用于接收要放大的信号的信号输入（Iin +，Iin-），提供放大信号的信号输出（Out），耦合在信号输入（Iin +，Iin-）之间的放大器级（AS） 以及信号输出（Out），具有耦合到信号输入（Iin +，Iin-））的输入的可切换动态偏置级（DB），具有耦合到信号输入（Iin +，Iin-）的输入的可切换增益提升级（GB） 以及耦合到放大器级（AS）的开关器件（SD），使得可切换动态偏置级（DB）的输出或可切换增益级级（GB）的输出端耦合到放大器 舞台（AS）。 在一个实施例中，通过借助于开关装置（SD），在放大的初始大信号相位中的可切换动态偏置级（DB）和放大的后一小信号相位中的可切换增益提升级（GB） 同时实现高增益和低电流消耗。 此外，提供了一种用于信号放大的方法。

    Operational amplifier
    6.
    发明公开
    Operational amplifier 失效
    运算放大器

    公开(公告)号：EP0696844A1

    公开(公告)日：1996-02-14

    申请号：EP95112614.3

    申请日：1995-08-10

    申请人： NEC CORPORATION

    发明人： Kato, Fumihiko, c/o NEC Corp.

    IPC分类号： H03F3/30

    CPC分类号： H03F3/3008 ,  H03F3/3001 ,  H03F3/4508 ,  H03F3/45179 ,  H03F2203/45036 ,  H03F2203/45188 ,  H03F2203/45224 ,  H03F2203/45274 ,  H03F2203/45281

    摘要： An operational amplifier includes an input stage supplied with an input signal and an output signal which responds to an intermediate signal from the input stage and produces an output signal at an output terminal. The output stage includes a first field effect or bipolar transistor coupled between a first power terminal and the output terminal and driven by the intermediate signal, a phase-inverting circuit responding to the intermediate signal and producing a phase-inverted signal, and a second field effect or bipolar transistor coupled between a second power terminal and the output terminal and driven by the phase-inverted signal, the first transistor having a channel type or a conductivity type equal to that of the second transistor.

    摘要翻译： 运算放大器包括输入级，输入级提供有输入信号和输出信号，该输出信号响应来自输入级的中间信号并在输出端产生输出信号。 输出级包括耦合在第一电源端和输出端之间并由中间信号驱动的第一场效应或双极晶体管，响应中间信号并产生相位反转信号的相位反转电路，以及第二场 耦合在第二电源端和输出端之间并由相位反转信号驱动的第一晶体管或双极性晶体管，第一晶体管的沟道类型或导电类型等于第二晶体管的沟道类型或导电类型。

    High gain differential amplifier capable of reducing offset voltage
    7.
    发明公开
    High gain differential amplifier capable of reducing offset voltage 失效
    具有高增益，能够DC的差分放大器的偏移电压的降低。

    公开(公告)号：EP0630102A3

    公开(公告)日：1995-08-23

    申请号：EP94304269.7

    申请日：1994-06-14

    申请人： NEC CORPORATION

    发明人： Sone, Kazuya, c/o NEC CORPORATION

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45179 ,  H03F3/45085 ,  H03F3/45089 ,  H03F3/45183 ,  H03F2203/45024 ,  H03F2203/45224 ,  H03F2203/45244 ,  H03F2203/45471 ,  H03F2203/45732

    摘要： A high gain differential amplifier including a differential transistor pair (M₁, M₂) having first and second transistors (M₁, M₂) whose gates are connected to first and second input terminals (t₁, t₂); a current mirror circuit wherein the drain of the transistor (M₁) is connected to an output terminal; a transistor (M₅) whose gate and drain are connected to the drain of transistor (M₁) and output terminal of the current mirror circuit, and to the output terminal (t₃) and the drain of transistor (M₂), respectively; a transistor (M₆) whose drain and gate are connected to an input terminal of the current mirror circuit, and to a bias power supply terminal, respectively; and constant-current source (I₁, I₂) which are connected to the common sources of differential transistor pair (M₁, M₂) and a source of the transistor (M₆), respectively. The addition of the sixth transistor (M₆) permits a voltage between the drain and source of the third and fourth transistors (M₃, M₄) to be nearly equal. As a result, a drain current ratio between the third and fourth transistors (M₃, M₄) can be precisely determined and thus an input offset voltage can be reduced to nearly zero.

    CMOS OPERATIONAL AMPLIFIER WITH REDUCED POWER DISSIPATION
    8.
    发明授权
    CMOS OPERATIONAL AMPLIFIER WITH REDUCED POWER DISSIPATION 失效
    具有降低功耗的CMOS操作放大器

    公开(公告)号：EP0037406B1

    公开(公告)日：1984-05-23

    申请号：EP80901914.4

    申请日：1980-09-02

    申请人： AMERICAN MICROSYSTEMS, INCORPORATED

    发明人： HAQUE, Yusuf Aminul

    IPC分类号： H03F3/16 ,  H03F3/45

    CPC分类号： H03F3/45179 ,  H03F3/3001 ,  H03F3/3008 ,  H03F3/3025 ,  H03F3/45183 ,  H03F2203/30018 ,  H03F2203/30033 ,  H03F2203/30036 ,  H03F2203/45188 ,  H03F2203/45224 ,  H03F2203/45508 ,  H03F2203/45674 ,  H03F2203/45692

    摘要： Operational amplifier (10) comprised of MOSFET elements which provides for a variable drive for an output stage (18) that results in lower power dissipation and increased gain factor over comparable circuits using constant bias drive for the output stage. A bias section (14) comprised of complementary MOS elements (24, 26) is connected to a single MOSFET (40) that furnishes constant current to the signal input section of a differential amplifier section (20). The output of this differential amplifier is furnished by one path directly to one complementary MOSFET element (72) of a high impedance output stage and by another path to a level shift section (16) which provides an output to a second complementary MOSFET element (80) of the output stage. Thus, the circuit functions under class A-B operation at low power dissipation and provides high open loop gain. Additional embodiments of the invention utilize three MOSFET elements (104, 106, 108) in the level shift section or an additional output stage having an NPN transistor (120) in combination with an N channel MOSFET (122).

    DRIVER CIRCUIT HAVING REDUCED CROSS-OVER DISTORTION
    9.
    发明公开
    DRIVER CIRCUIT HAVING REDUCED CROSS-OVER DISTORTION 失效
    具有减少空PASSAGE失真驱动电路。

    公开(公告)号：EP0066572A1

    公开(公告)日：1982-12-15

    申请号：EP81902936.0

    申请日：1981-10-28

    申请人： MOTOROLA, INC.

    发明人： WHATLEY, Roger A.

    IPC分类号： H03F1 ,  H03F3

    CPC分类号： H03F3/45179 ,  H03F1/3205 ,  H03F3/3008 ,  H03F2203/30021 ,  H03F2203/45224

    摘要： Un circuit de commande (10) approprie a une utilisation dans un amplificateur operationnel, comprend un transistor de redressement bipolaire (36) qui envoie un courant a une borne de sortie (38) proportionnellement a un courant de commande applique, et un transistor de rabaissement MOS (48) qui affaiblit le courant provenant de la borne de sortie (38) proportionnellement a une tension de commande appliquee. Un transistor de commande MOS (32) fournit un courant de commande constant pour le transistor de redressement (36), et un transistor de shuntage MOS (44) shunte le courant de commande en l'eloignant du transistor bipolaire (36) proportionnellement a la tension de commande. Un circuit de compensation de convergence (14) developpe une tension de polarisation predeterminee sur la base du transistor bipolaire (36) par rapport a la tension sur la borne de sortie (38) pour assurer un niveau minimum de fonctionnement du transistor bipolaire (36) lorsque la borne de sortie (38) est proche de la tension de terre analogique.