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公开(公告)号:EP0072751A2
公开(公告)日:1983-02-23
申请号:EP82401522.6
申请日:1982-08-11
IPC分类号: H03L7/08
CPC分类号: H03L7/0895
摘要: The phase-locked loop circuit provides a phase comparator which receives input signals through a first input terminal, a loop filter which receives a first output and a second output of the phase comparator, and a voltage-controlled oscillator which produces output signals of an oscillation frequency proportional to the first output and the second output of the loop filter, the signals corresponding to output signals produced by the voltage-controlled oscillator being supplied to a second input terminal of the phase comparator so that the phase of the signals supplied to the first input terminal of the phase comparator is compared with the phase of the signals supplied to the second input terminal. In the present invention, the loop filter comprise a first capacitor connected to the output terminal of the loop filter, a second capacitor and a third capacitor each having a terminal connected to the output terminal of the loop filter, a charging circuit for electrically charging the first, second, and third capacitors, the charging circuit being connected in parallel with the second capacitor, and a discharging circuit for discharging the first, second, and third capacitors, the discharging circuit being connected in parallel with the third capacitor.
摘要翻译: 锁相环电路提供一个相位比较器,它通过第一输入端接收输入信号,一个接收相位比较器的第一输出和第二输出的环路滤波器,以及产生振荡输出信号的压控振荡器 频率与环路滤波器的第一输出和第二输出成比例,对应于由压控振荡器产生的输出信号的信号被提供给相位比较器的第二输入端,使得提供给第一 将相位比较器的输入端与提供给第二输入端的信号的相位进行比较。 在本发明中 环路滤波器包括连接到环路滤波器的输出端的第一电容器,第二电容器和第三电容器,每个电容器具有连接到环路滤波器的输出端子的端子;充电电路,用于对第一,第二和/ 第三电容器,充电电路与第二电容器并联连接;以及放电电路,用于对第一,第二和第三电容器进行放电,放电电路与第三电容器并联连接。
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公开(公告)号:EP0072751B1
公开(公告)日:1986-01-08
申请号:EP82401522.6
申请日:1982-08-11
IPC分类号: H03L7/08
CPC分类号: H03L7/0895
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公开(公告)号:EP0173983B1
公开(公告)日:1992-12-30
申请号:EP85110978.5
申请日:1985-08-30
申请人: FUJITSU LIMITED
发明人: Okazaki, Takeshi , Tsuda, Toshitaka 3-304, Minaminomachi , Maki, Shinichi Moegino Haitsu 105 , Matsuda, Kiichi Shibue-so 7 , Gambe, Hirohisa , Fukui, Hirokazu , Ikezawa, Toshi
IPC分类号: H03M3/04
CPC分类号: H03M7/3044 , G06T9/004
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公开(公告)号:EP0407962A3
公开(公告)日:1992-12-23
申请号:EP90113148.2
申请日:1990-07-10
申请人: FUJITSU LIMITED
发明人: Chujo, Kaoru , Kakuishi, Mitsuo , Fukui, Hirokazu
IPC分类号: H04B3/23
摘要: An adaptive echo canceller for suppressing an echo in an input signal by a pseudo echo, includes a pseudo echo generation filter (11) having a predicted impulse response sequence of an echo path as filter coefficients thereof for generating a pseudo echo, a coefficient renewal part (12, 4A) for adaptively renewing the filter coefficients of the pseudo echo generation filter, and a part for suppressing an echo by the pseudo echo which is generated by the pseudo echo generation filter. The coefficient renewal part includes a part (48) for dividing renewed filter coefficients into a plurality of groups each having a certain number of renewed filter coefficients, and a part (48, 49₁, 49₂, 47) for successively selecting one group with a predetermined period and carrying out a correction process with respect to the renewed filter coefficients within the selected group, where the correction process corrects an accumulation of errors of renewal processes.
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公开(公告)号:EP0407962B1
公开(公告)日:1995-09-27
申请号:EP90113148.2
申请日:1990-07-10
申请人: FUJITSU LIMITED
发明人: Chujo, Kaoru , Kakuishi, Mitsuo , Fukui, Hirokazu
IPC分类号: H04B3/23
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公开(公告)号:EP0407962A2
公开(公告)日:1991-01-16
申请号:EP90113148.2
申请日:1990-07-10
申请人: FUJITSU LIMITED
发明人: Chujo, Kaoru , Kakuishi, Mitsuo , Fukui, Hirokazu
IPC分类号: H04B3/23
摘要: An adaptive echo canceller for suppressing an echo in an input signal by a pseudo echo, includes a pseudo echo generation filter (11) having a predicted impulse response sequence of an echo path as filter coefficients thereof for generating a pseudo echo, a coefficient renewal part (12, 4A) for adaptively renewing the filter coefficients of the pseudo echo generation filter, and a part for suppressing an echo by the pseudo echo which is generated by the pseudo echo generation filter. The coefficient renewal part includes a part (48) for dividing renewed filter coefficients into a plurality of groups each having a certain number of renewed filter coefficients, and a part (48, 49₁, 49₂, 47) for successively selecting one group with a predetermined period and carrying out a correction process with respect to the renewed filter coefficients within the selected group, where the correction process corrects an accumulation of errors of renewal processes.
摘要翻译: 一种用于通过伪回波抑制输入信号中的回波的自适应回波消除器包括具有作为其用于产生伪回声的滤波器系数的回波路径的预测脉冲响应序列的伪回波产生滤波器(11),系数更新部分 (12,4A),用于自适应地更新伪回波产生滤波器的滤波器系数,以及用于通过伪回波产生滤波器产生的伪回波抑制回波的部分。 系数更新部分包括用于将更新的滤波器系数分成多个组的部分(48),每个组具有一定数量的更新的滤波器系数;以及部分(48,491,492,47),用于连续地选择具有预定 对所选择的组中的更新的滤波器系数执行校正处理,其中校正过程校正更新处理的错误的累积。
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公开(公告)号:EP0072751A3
公开(公告)日:1983-08-24
申请号:EP82401522
申请日:1982-08-11
IPC分类号: H03L07/08
CPC分类号: H03L7/0895
摘要: The phase-locked loop circuit provides a phase comparator which receives input signals through a first input terminal, a loop filter which receives a first output and a second output of the phase comparator, and a voltage-controlled oscillator which produces output signals of an oscillation frequency proportional to the first output and the second output of the loop filter, the signals corresponding to output signals produced by the voltage-controlled oscillator being supplied to a second input terminal of the phase comparator so that the phase of the signals supplied to the first input terminal of the phase comparator is compared with the phase of the signals supplied to the second input terminal. In the present invention, the loop filter comprise a first capacitor connected to the output terminal of the loop filter, a second capacitor and a third capacitor each having a terminal connected to the output terminal of the loop filter, a charging circuit for electrically charging the first, second, and third capacitors, the charging circuit being connected in parallel with the second capacitor, and a discharging circuit for discharging the first, second, and third capacitors, the discharging circuit being connected in parallel with the third capacitor.
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公开(公告)号:EP0173983A3
公开(公告)日:1988-06-08
申请号:EP85110978
申请日:1985-08-30
申请人: FUJITSU LIMITED
发明人: Okazaki, Takeshi , Tsuda, Toshitaka 3-304, Minaminomachi , Maki, Shinichi Moegino Haitsu 105 , Matsuda, Kiichi Shibue-so 7 , Gambe, Hirohisa , Fukui, Hirokazu , Ikezawa, Toshi
IPC分类号: H03M03/04
CPC分类号: H03M7/3044 , G06T9/004
摘要: A differential coding circuit including a subtractor (7,8). a quantizer (3) for quantizing a differential signal (D) from the subtractor (1), and a predicted signal generating circuit (4,5,6) for generating a predicted signal on the basis of a quantized differential signal from the quantizer (3). The subtractor (7,8) subtracts the quantized differential signal of the quantizer (3) and the predicted signal from the sampled input signal (A). The critical path of the circuit is shortened, therefore the operation speed of the differential coding circuit increases.
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公开(公告)号:EP0173983A2
公开(公告)日:1986-03-12
申请号:EP85110978.5
申请日:1985-08-30
申请人: FUJITSU LIMITED
发明人: Okazaki, Takeshi , Tsuda, Toshitaka 3-304, Minaminomachi , Maki, Shinichi Moegino Haitsu 105 , Matsuda, Kiichi Shibue-so 7 , Gambe, Hirohisa , Fukui, Hirokazu , Ikezawa, Toshi
IPC分类号: H03M3/04
CPC分类号: H03M7/3044 , G06T9/004
摘要: A differential coding circuit including a subtractor (7,8). a quantizer (3) for quantizing a differential signal (D) from the subtractor (1), and a predicted signal generating circuit (4,5,6) for generating a predicted signal on the basis of a quantized differential signal from the quantizer (3). The subtractor (7,8) subtracts the quantized differential signal of the quantizer (3) and the predicted signal from the sampled input signal (A). The critical path of the circuit is shortened, therefore the operation speed of the differential coding circuit increases.
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