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公开(公告)号：EP2963826A1
公开(公告)日：2016-01-06
申请号：EP14175817.7
申请日：2014-07-04
申请人： NXP B.V.
发明人： Saric, Tarik , Drago, Salvatore
CPC分类号： H03K3/0315 , H03L7/099 , H03L7/22 , H03L2207/06 , H04B1/16
摘要： The invention relates to frequency synthesiser circuits, and in particular to frequency synthesiser circuits characterised by a small channel spacing. Embodiments disclosed include a frequency synthesiser circuit (100) for a radio receiver, the circuit comprising: a digitally controlled oscillator (118) configured to generate an output signal (128) with an output frequency on application of an oscillator enable signal (126); a delay module (160; 210) configured to delay an input reference signal (142) to generate a delayed reference signal (144; 244); and a duty cycle module (150) configured to modulate the oscillator enable signal based on a period of an input reference signal (142) and the delay of the delayed reference signal (144), such that a ratio between the output frequency and the frequency of the input reference signal (142) is a non-integer.
摘要翻译： 本发明涉及频率合成器电路，特别涉及以小信道间隔为特征的频率合成器电路。 所公开的实施例包括用于无线电接收机的频率合成器电路（100），该电路包括：数字控制振荡器（118），被配置为在施加振荡器使能信号（126）时产生具有输出频率的输出信号（128）。 延迟模块（160; 210），被配置为延迟输入参考信号（142）以产生延迟的参考信号（144; 244）; 以及占空比模块（150），被配置为基于输入参考信号（142）的周期和延迟的参考信号（144）的延迟来调制振荡器使能信号，使得输出频率和频率之间的比率 的输入参考信号（142）是非整数。
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公开(公告)号：EP4372404A1
公开(公告)日：2024-05-22
申请号：EP22207713.3
申请日：2022-11-16
申请人： NXP B.V.
IPC分类号： G01S7/35 , G01S13/34 , G01S13/58 , G01S13/931
CPC分类号： G01S13/584 , G01S7/356 , G01S13/931 , G01S13/34
摘要： A radar sensor comprising a chirp generator that is configured to provide radar signalling for transmission. The radar signalling comprises a sequence of radar chirps, and wherein each radar chirp has a chirp slope that defines the rate of change of frequency in the radar chirp. A mixer multiplies the transmitted radar signalling with a received, reflected version of the transmitted radar signalling in order to provide analogue intermediate frequency, IF, signalling. An ADC samples the IF signalling in order to generate digital signalling. A digital processor populates a 2-dimensional array of bin-values based on the digital-values, such that: a first axis of the 2-dimensional array is a fast time axis and a second axis of the 2-dimensional array is a slow time axis. A chirp slope frequency adjuster sets the chirp slope of the radar chirps based on an index in the sequence of radar chirps. The digital processor performs DFT calculations on the bin-values in the 2-dimensional array along the fast time axis and the slow time axis in order to determine the range and velocity of any detected objects.
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3.发明公开FREQUENCY SYNTHESIZER CIRCUIT WITH LINEARIZED GAIN OF THE CONTROLLED OSCILLATOR 审中-公开FREQUENZSYNTHESIZERSCHALTUNG MIT LINEARISIERTERVERSTÄRKUNGDES GESTEURTEN OSZILLATORS
公开(公告)号：EP3107213A1
公开(公告)日：2016-12-21
申请号：EP15172783.1
申请日：2015-06-18
申请人： NXP B.V.
CPC分类号： H03L7/107 , G01S7/032 , G01S13/343 , G01S13/345 , G01S13/931 , H03B23/00 , H03L7/0891 , H03L7/093 , H03L7/099 , H03L7/1974 , H03L7/1976
摘要： A frequency synthesizer circuit (100) for a car radar system is disclosed, the circuit (100) comprising: a phase locked loop (110) for providing a frequency chirp at a range of tuning voltages (140, 320), said phase locked loop (110) comprising: a phase detector (122) and a voltage controlled oscillator (150), wherein said phase locked loop (110) has an open loop gain dependent on the tuning voltage (140) and a gain of the voltage controlled oscillator (150); a first varactor (340, 410) unit for altering the gain (392) of the voltage controlled oscillator (150) over a first subset range of tuning voltages (344); and a second varactor (360, 430) unit for altering the gain (392) of the voltage controlled oscillator (150) over a second subset range of tuning voltages (364), wherein the second subset range of tuning voltages (364) is higher than the first subset range of tuning voltages (344); such that variations in the open loop gain (384, 394) over the first and second subset range of tuning voltages (344, 364) of the range of tuning voltages (320) are compensated for by the varactor units (340, 360).
摘要翻译： 公开了一种用于汽车雷达系统的频率合成器电路（100），所述电路（100）包括：锁相环（110），用于在调谐电压（140,320）的范围内提供频率啁啾，所述锁相环 （110），包括：相位检测器（122）和压控振荡器（150），其中所述锁相环（110）具有取决于调谐电压（140）的开环增益和压控振荡器 150）; 第一变容二极管（340,410）单元，用于在调谐电压的第一子范围（344）上改变压控振荡器（150）的增益（392）; 以及第二变容二极管（360,430）单元，用于在调谐电压（364）的第二子范围上改变压控振荡器（150）的增益（392），其中调谐电压（364）的第二子范围更高 比第一子集调谐电压范围（344）; 使得在调谐电压（320）范围内的调谐电压（344,364）的第一和第二子集范围内的开环增益（384,394）的变化由变容二极管单元（340,360）补偿。
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4.发明公开Two-point modulation of a semi-digital phase locked loop 审中-公开Zwei-Punkt调制einer Halbdigitalen Phasenregelschleife
公开(公告)号：EP3059866A1
公开(公告)日：2016-08-24
申请号：EP15155328.6
申请日：2015-02-17
申请人： NXP B.V.
CPC分类号： H04B1/7073 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0958 , H03C3/0991 , H03L7/1976 , H04B2001/6912 , H04B2201/7073
摘要： A phase locked loop is disclosed having a frequency controlled oscillator (42), a feedback path, a time to digital converter (10) and a memory. The frequency controlled oscillator (42) comprises a first control input (135, 136) for varying the frequency of the output (106) of the frequency controlled oscillator (42) so as to track a reference frequency (101) and a second control input (139) for modulating the frequency of the output signal (106) so as to produce a chirp. The feedback path is configured to provide an input signal (107) to the time to digital converter (10), and comprises modulation cancelling module (14) operable to remove the frequency modulation resulting from the second control input (139) from the output signal (106). The memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in the response of the frequency controlled oscillator to the second control input (139). The phase locked loop is operable in a chirp mode, in which the second control input (139) is produced by determining a value for the second control input (139) corresponding with a desired chirp frequency based on the stored second control input values in the memory, and in which the phase locked loop is configured to determine the first control input (135, 136) based on the feedback path from which the modulation cancelling module (14) has removed the frequency modulation resulting from the second control input (139).
摘要翻译： 公开了一种具有频率控制振荡器（42），反馈路径，时间到数字转换器（10）和存储器的锁相环。 频率控制振荡器（42）包括用于改变频率控制振荡器（42）的输出（106）的频率的第一控制输入（135,136），以便跟踪参考频率（101）和第二控制输入 （139），用于调制输出信号（106）的频率，以产生啁啾。 反馈路径被配置为向时间到数字转换器（10）提供输入信号（107），并且包括调制解除模块（14），其可操作以从输出信号中去除由第二控制输入（139）产生的频率调制 （106）。 存储器存储每个对应于期望啁啾频率并且补偿频率控制振荡器对第二控制输入（139）的响应中的非线性的第二控制输入值。 锁相环可以在线性调频模式下操作，其中通过基于所存储的第二控制输入值确定对应于期望啁啾频率的第二控制输入（139）的值来产生第二控制输入（139） 存储器，并且其中所述锁相环被配置为基于所述调制消除模块（14）从其中去除了由所述第二控制输入（139）产生的频率调制的反馈路径来确定所述第一控制输入（135,136） 。
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5.发明公开
公开(公告)号：EP3059857A1
公开(公告)日：2016-08-24
申请号：EP15155327.8
申请日：2015-02-17
申请人： NXP B.V.
CPC分类号： G04F10/005 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03L7/085 , H03L7/0992 , H03L7/1974 , H03L7/1976 , H03M1/38
摘要： A time to digital converter (10) is disclosed. The time to digital converter (10) comprises: a synchronisation block (20) configured to output a voltage pulse (110) with duration based on a time difference between a reference oscillating signal (101) and an input oscillating signal (107); a charge pump (41) arranged to receive the voltage pulse (110) and to convert the voltage pulse into a current pulse; an integrator (50) comprising an integrator capacitor (24, 25), the integrator (50) being configured to receive the current pulse (110) and integrate the current pulse (110) as a charge on the integrator capacitor (24, 25), resulting in an integrator output voltage (115); and a successive approximation register (40) configured to determine the integrator output voltage (115) with respect to a reference voltage by adjusting the charge on the integrator capacitor (24, 25) so as to reduce the integrator output voltage (115) to within a least significant bit (D0) of a reference voltage by successive approximation, and configured to output the determined integrator output voltage (115) as a digital signal (125). A phase locked loop comprising the time to digital converter (10) is disclosed.
摘要翻译： 公开了一种数字转换器（10）。 数字转换器（10）的时间包括：同步块（20），被配置为基于参考振荡信号（101）和输入振荡信号（107）之间的时间差输出具有持续时间的电压脉冲（110）; 布置成接收电压脉冲（110）并将电压脉冲转换成电流脉冲的电荷泵（41）; 积分器（50），包括积分器电容器（24,25），所述积分器（50）被配置为接收所述电流脉冲（110）并且将所述电流脉冲（110）作为所述积分电容器（24,25）上的电荷进行积分， ，导致积分器输出电压（115）; 以及逐次逼近寄存器（40），被配置为通过调整积分器电容器（24,25）上的电荷来相对于参考电压来确定积分器输出电压（115），以便将积分器输出电压（115）降低到内部 通过逐次逼近的参考电压的最低有效位（D0），并且被配置为输出所确定的积分器输出电压（115）作为数字信号（125）。 公开了一种包括时间数字转换器（10）的锁相环。
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公开(公告)号：EP4296717A1
公开(公告)日：2023-12-27
申请号：EP23173470.8
申请日：2023-05-15
申请人： NXP B.V.
发明人： Gibas, Piotr , Saric, Tarik
摘要： A radar system injects a calibrated current at a signal generator during a reset portion and acquisition portion of each chirp period. The signal generator employs "gear-switching" to reduce PLL bandwidth during an acquisition phase and to increase the phase lock loop (PLL) bandwidth during a reset phase. By employing gear switching to change the bandwidth of the PLL circuit during the different portions of each chirp period, the length of the reset period is reduced, thus improving overall efficiency of the radar system while maintaining good performance.
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公开(公告)号：EP3770629A1
公开(公告)日：2021-01-27
申请号：EP20185767.9
申请日：2020-07-14
申请人： NXP B.V.
摘要： Aspects of the present disclosure are directed to injection locking (320) and related apparatuses. As may be implemented in accordance with one or more embodiments, an apparatus includes a plurality of injection-locking circuits configured to receive an injection signal, each injection-locking circuit (320) including a mixer and a lock-detection circuit. In each of the injection-locking circuits, the lock-detection circuit detects a lock-status relationship between the injection signal (320in) and a signal output from the injection-locking circuit (330out). In response to the lock-status relationship indicating an unlocked condition, a phase/magnitude of the injection signal is adjusted. In response to the lock-status relationship indicating a locked condition, transmission (330out) of an FM continuous wave (FMCW) chirp signal (310) is facilitated.
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公开(公告)号：EP3343773A1
公开(公告)日：2018-07-04
申请号：EP16207366.2
申请日：2016-12-29
申请人： NXP B.V.
CPC分类号： H03B5/1243 , H03B5/1212 , H03B5/1262 , H03C3/0925 , H03L7/099 , H03L7/197 , H03L2207/06
摘要： A chirp-generator comprising a phase-detector for providing a phase-difference-signal representative of a phase difference between a clock-input-signal and a feedback-signal. A VCO-circuit is configured to provide a chirp-generator-output-signal based on the phase-difference-signal. The VCO-circuit comprises a switched-varactor-bank, which includes a plurality of varactors, and a varactor-switch associated with each of the plurality of varactors. The varactor-switch is configured to selectively control whether or not the associated varactor contributes to the capacitance of the VCO-circuit, based on the state of a varactor-control-signal. The chirp-generator also includes a feedback-component configured to: receive the chirp-generator-output-signal; and apply a variable-multiplication-factor to the chirp-generator-output-signal in order to provide the feedback signal for the phase-detector. A controller provides a sequence of different variable-multiplication-factors to the feedback-component; and provides varactor-control-signals to the plurality of varactors such that the varactors are sequentially controlled such that they contribute to the capacitance of the VCO-circuit.
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