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    Integrated circuit I/O using a high performance bus interface
    3.
    发明公开
    Integrated circuit I/O using a high performance bus interface 无效
    集成电路I / O采用高性能总线接口

    公开(公告)号：EP1816569A2

    公开(公告)日：2007-08-08

    申请号：EP06125946.1

    申请日：1991-04-16

    申请人： RAMBUS INC.

    发明人： Farmwald, Michael ,  Horowitz, Mark

    IPC分类号： G06F13/16

    CPC分类号： G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    摘要： The present invention includes a system comprising a bus that includes a plurality of bus lines for carrying substantially all address, data and control information needed by each semiconductor device coupled to the bus for communication with substantially every other semiconductor device connected to the bus, wherein the bus uses address multiplexing to convey a single memory address, a plurality of synchronous dynamic random access memory (DRAM) semiconductor devices coupled to the bus, each DRAM of the plurality of synchronous DRAM semiconductor devices including connection means adapted to connect the DRAM to the bus, clock receiver circuitry for receiving a clock signal, a programmable access-time register for storing a value which is representative of a number of clock cycles of the clock signal to transpire after which the DRAM responds to a read request received synchronously with respect to the clock signal, the programmable access-time register being accessible to the bus through the connection means, wherein data is provided to the programmable access-time register over the bus to set the value in the programmable access-time register, a plurality of output drivers for outputting data onto the bus in response to the read request, wherein the output drivers output the data on the bus after the number of clock cycles of the clock signal transpire and synchronously with respect to the clock signal; so that the read request and the corresponding response are separated by the number of clock cycles as selected by the value stored in the programmable access-time register, wherein each output driver of the plurality of output drivers outputs the data onto the bus at a bus cycle data rate that is twice the rate of the clock signal, sense amplifiers used for reading the data from the memory array, wherein when precharge information received over the bus as a part of the read request indicates that a precharge operation should be performed, automatically precharging the sense amplifiers as a part of execution of the read request, and wherein when the precharge information indicates that a precharge operation should not be performed, holding the data in the sense amplifiers; and a master device coupled to the bus, wherein the master provides the value stored in the programmable access time register, issues the read request that includes precharge information, and receives the data output in response to the read request at the bus cycle data rate after the number of clock cycles as selected by the value stored in the programmable access time register.

    摘要翻译： 本发明包括一个系统，该系统包括一个总线，该总线包括多条总线，用于传送与总线耦合的每个半导体器件所需的基本上所有的地址，数据和控制信息，以便与连接到总线的基本上每一个其他半导体器件进行通信， 总线使用地址多路复用来传送单个存储器地址，耦合到总线的多个同步动态随机存取存储器（DRAM）半导体器件，多个同步DRAM半导体器件中的每个DRAM包括适于将DRAM连接到总线的连接装置 ，用于接收时钟信号的时钟接收器电路，用于存储代表要发送的时钟信号的时钟周期数量的值的可编程存取时间寄存器，在此之后，DRAM响应于关于 时钟信号，可编程存取时间寄存器可被总线thr访问 只要连接装置通过总线将数据提供给可编程存取时间寄存器以设置可编程存取时间寄存器中的值，多个输出驱动器用于响应于读取请求将数据输出到总线上，其中 输出驱动器在时钟信号发送的时钟周期数之后并且与时钟信号同步地在总线上输出数据; 使得读请求和相应的响应由存储在可编程存取时间寄存器中的值所选择的时钟周期数分开，其中多个输出驱动器中的每个输出驱动器在总线上将数据输出到总线 用于从存储器阵列中读取数据的读出放大器，其中当作为读取请求的一部分通过总线接收到的预充电信息指示应该执行预充电操作时，自动地 将读出放大器预充电为执行读取请求的一部分，并且其中当预充电信息指示不应执行预充电操作时，将数据保持在读出放大器中; 以及耦合到总线的主设备，其中主设备提供存储在可编程存取时间寄存器中的值，发出包括预充电信息的读请求，并且在总线周期数据速率响应于读请求接收数据输出之后 由存储在可编程访问时间寄存器中的值选择的时钟周期数。

    Dynamic random access memory (DRAM) semiconductor device
    9.
    发明公开
    Dynamic random access memory (DRAM) semiconductor device 无效
    Halbleiterbauelement mit dynamischem Arbeitsspeicher（DRAM）

    公开(公告)号：EP1640847A2

    公开(公告)日：2006-03-29

    申请号：EP05026720.2

    申请日：1991-04-16

    申请人： Rambus, Inc.

    发明人： Farmwald, Michael ,  Horowitz, Mark

    IPC分类号： G06F1/04

    CPC分类号： G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    摘要： The present invention concerns a dynamic random access memory (DRAM) semiconductor device having at least one memory array which includes a plurality of memory cells arranged in rows and columns. The DRAM contains connection means adapted to connect the DRAM to an external bus which is a part of a semiconductor bus architecture. The semiconductor bus architecture includes a plurality of semiconductor devices connected in parallel to the external bus. The external bus includes a plurality of bus lines for carrying substantially all address, data, and control information needed by the DRAM for communication with substantially every other semiconductor device connected to the external bus. The connection means is adapted to receive multiplexed addresses. The DRAM contains clock receiver circuitry for receiving an external clock signal. It further contains a programmable access-time register for storing a value which is representative of a first number of clock cycles of the external clock signal to transpire after which the DRAM responds to a write request received synchronously with respect to the external clock signal. The programmable access-time register is accessible to the external bus through the connection means. In order to set the value in the programmable access-time register, data is transmitted to the programmable access-time register over the external bus. The DRAM contains further a plurality of input receivers to receive write data from the external bus in response to the write request. The input receivers input the write data from the external bus after the first number of clock cycles transpire so that the write request and the corresponding receipt of write data are separated by the first number of clock cycles as selected by the value stored in the programmable access-time register.

    摘要翻译： 本发明涉及具有至少一个存储器阵列的动态随机存取存储器（DRAM）半导体器件，其包括以行和列排列的多个存储器单元。 DRAM包含适于将DRAM连接到作为半导体总线架构的一部分的外部总线的连接装置。 半导体总线架构包括与外部总线并联连接的多个半导体器件。 外部总线包括用于承载DRAM所需的基本上所有地址，数据和控制信息的多条总线，用于与连接到外部总线的基本上每个其他半导体器件进行通信。 连接装置适于接收复用的地址。 DRAM包含用于接收外部时钟信号的时钟接收器电路。 它还包含可编程存取时间寄存器，用于存储表示外部时钟信号的第一数量的时钟周期数值的值，之后DRAM响应于相对于外部时钟信号同步接收的写入请求。 可编程访问时间寄存器可通过连接方式访问外部总线。 为了设置可编程访问时间寄存器中的值，数据通过外部总线传输到可编程访问时间寄存器。 DRAM还包括多个输入接收器，以响应写入请求从外部总线接收写入数据。 输入接收器在第一数量的时钟周期之后输入来自外部总线的写入数据，使得写入请求和写入数据的对应接收被存储在可编程访问中的值所选择的第一数量的时钟周期分隔开 时间注册