公开(公告)号：EP0536992B1

公开(公告)日：1998-05-13

申请号：EP92309133.4

申请日：1992-10-07

申请人： SGS-THOMSON MICROELECTRONICS, INC.

发明人： Huang, Kuei-Wu

IPC分类号： H01L21/768

CPC分类号： H01L21/31056 ,  H01L21/76819

公开(公告)号：EP0549261A1

公开(公告)日：1993-06-30

申请号：EP92311509.1

申请日：1992-12-16

申请人： SGS-THOMSON MICROELECTRONICS, INC.

发明人： Huang, Kuei-Wu

IPC分类号： H01L21/90

CPC分类号： H01L21/76877 ,  H01L21/7684

摘要： A thin conductive layer (20) is formed over an underlying structure in an integrated circuit. The underlying structure can be either a semiconductor substrate (20) or an interlevel interconnect signal line (18). An insulating layer (22) is deposited over the device. The insulating layer (22) is patterned and etched in order to expose a portion (24,26) of the underlying conductive layer (20) and to define an interconnect signal line. When the signal line locations are etched away, the thin conductive layer (20) acts as an etch stop and protects the underlying structure. A metal refill process can be used to then form interconnects and contacts within the etched interconnect lines. This results in interconnect and contacts having upper surfaces which are substantially coplanar with the upper surface of the insulating layer (22) in which they are formed.

摘要翻译： 在集成电路中的下层结构之上形成薄导电层（20）。 底层结构可以是半导体衬底（20）或层间互连信号线（18）。 绝缘层（22）沉积在器件上。 图案化和蚀刻绝缘层（22）以暴露下面的导电层（20）的部分（24,26）并限定互连信号线。 当信号线位置被蚀刻掉时，薄导电层（20）用作蚀刻停止并保护下面的结构。 可以使用金属填充工艺来在蚀刻的互连线内形成互连和接触。 这导致互连和触点具有与形成它们的绝缘层（22）的上表面基本共面的上表面。

公开(公告)号：EP0558260A1

公开(公告)日：1993-09-01

申请号：EP93301304.7

申请日：1993-02-23

申请人： SGS-THOMSON MICROELECTRONICS, INC.

发明人： Huang, Kuei-Wu

IPC分类号： H01L21/90 ,  H01L21/311

CPC分类号： H01L21/76802

摘要： A method for forming contact vias (34,36) in a integrated circuit (10) which do not have planarizing material nearby. After a first insulating layer (16) is deposited over the integrated circuit, a planarizing layer (18) is deposited over the first insulating layer. The planarizing layer (18) is etched back and portions of the planarizing layer (18) may remain in the lower topographical regions of the first insulating layer (16) to planarize the surface of the integrated circuit. A first masking layer (20) is then formed over the surface of the integrated circuit (10). The openings (22,24) created in the first masking layer have a size which is greater than the size of the contact vias to be formed. The first insulating layer (16) is partially etched into so that portions of the planarizing layer (18) near the locations of the contact vias (22,24) are removed. The first masking layer (20) is then removed, and a second insulating layer (26) is deposited over the integrated circuit (10). A second masking layer (28) having openings (30,32) which define the locations of the contact vias (34,36) to be created is then formed over the second insulating layer (26). The size of the openings (30,32) in the second masking layer (28) are smaller than the size of the openings (22,24) in the first masking layer (20). The contact vias (34,36) are then formed through the first and second insulating layers (26,18).

摘要翻译： 一种在不具有平面化材料的集成电路（10）中形成接触孔（34,36）的方法。 在集成电路上沉积第一绝缘层（16）之后，在第一绝缘层上沉积平坦化层（18）。 平坦化层（18）被回蚀刻，并且平坦化层（18）的部分可以保留在第一绝缘层（16）的下部形貌区域中，以使集成电路的表面平坦化。 然后在集成电路（10）的表面上形成第一掩模层（20）。 在第一掩模层中形成的开口（22,24）的尺寸大于要形成的接触孔的尺寸。 部分地蚀刻第一绝缘层（16），使得在接触通孔（22,24）的位置附近的平坦化层（18）的部分被去除。 然后去除第一掩模层（20），并且在集成电路（10）上沉积第二绝缘层（26）。 然后，在第二绝缘层（26）上形成具有限定所形成的接触孔（34,36）的位置的开口（30,32）的第二掩模层（28）。 第二掩模层（28）中的开口（30,32）的尺寸小于第一掩模层（20）中的开口（22,24）的尺寸。 接触通孔（34,36）然后通过第一和第二绝缘层（26,18）形成。

公开(公告)号：EP0536992A3

公开(公告)日：1993-05-26

申请号：EP92309133.4

申请日：1992-10-07

申请人： SGS-THOMSON MICROELECTRONICS, INC.

发明人： Huang, Kuei-Wu

IPC分类号： H01L21/90

CPC分类号： H01L21/31056 ,  H01L21/76819

摘要： A method for planarizing an integrated circuit structure having a glass layer (15) overlying an oxide layer (13) 0f an integrated circuit is presented. The method includes the steps of selectively etching portions of the glass (15) structure that overlie portions of the oxide layer (13) that have higher elevations than other portions of the oxide layer (13), and then etching the glass layer (15) overall. The etching step includes forming a layer of photoresist (17) over the glass layer (15), exposing selected areas (20) of the photoresist (17) over the portions of the oxide layer (13) that have higher elevations than other portions of the oxide layer (13), removing the exposed areas of the photoresist (17), and etching the glass layer (15) within the removed areas of the photoresist. The mask used in patterning the photoresist can be the same mask, or its negative, that is used in forming the metalization layer (11) over which the oxide (13) and glass layers (15) have been formed. Additionally, an integrated circuit structure is presented that includes a substrate (10) in which integrated circuit elements are constructed, a first interconnection metalization (11) over the substrate (10) interconnecting selected ones of the integrated circuit elements, and an oxide layer (13) over the substrate (10) and the first metal interconnection pattern (11). A glass layer (15) over the oxide layer (13) is substantially planar between portions that overlie the metalization (11) and portions that do not over lie the metalization (11).

公开(公告)号：EP0747946A2

公开(公告)日：1996-12-11

申请号：EP96303951.6

申请日：1996-05-31

申请人： SGS-THOMSON MICROELECTRONICS, INC.

发明人： Huang, Kuei-Wu ,  Chan, Tsiu C. ,  Smith, Gregory C.

IPC分类号： H01L21/762 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L21/28123 ,  H01L21/762 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/42316 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833

摘要： A method is provided for forming an improved planar structure of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide is grown across the integrated circuit patterned and etched to form an opening with substantially vertical sidewalls exposing a portion of an upper surface of a substrate underlying the field oxide where an active area will be formed. A gate electrode comprising a polysilicon gate electrode and a gate oxide are formed over the exposed portion of the substrate. The polysilicon gate has a height at its upper surface above the substrate at or above the height of the upper surface of the field oxide. The gate electrode preferably also comprises a silicide above the polysilicon and an oxide capping layer above the silicide. LDD regions are formed in the substrate adjacent the gate electrode and sidewall spacers are formed along the sides of the gate electrode including the silicide and the capping layer.

公开(公告)号：EP0564136B1

公开(公告)日：1998-06-03

申请号：EP93302155.2

申请日：1993-03-22

申请人： SGS-THOMSON MICROELECTRONICS, INC.

发明人： Lin, Yih-Shung ,  Huang, Kuei-Wu ,  Lu, Lun-Tseng

IPC分类号： H01L21/768 ,  H01L21/3105

CPC分类号： H01L21/76819

公开(公告)号：EP0564191A3

公开(公告)日：1994-11-02

申请号：EP93302375.6

申请日：1993-03-26

申请人： SGS-THOMSON MICROELECTRONICS, INC.

发明人： Bryant, Frank R. ,  Chan, Tsui C. ,  Huang, Kuei-Wu

IPC分类号： H01L21/82 ,  H01L23/544 ,  H01L27/092 ,  H01L21/76

CPC分类号： H01L21/823892 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method is provided for fabricating an integrated circuit having an N-type well and a P-type well, with the upper surfaces of the N-type well and the P-type well coplanar. An insulating layer is formed over the integrated circuit. A first masking layer is formed over the insulating layer to define locations of a first well to be formed. An impurity of a first conductivity type is implanted into the semiconductor substrate of the integrated circuit to form a first region. The first masking layer is removed, and a second masking layer is formed over the insulating layer to define locations of a second well to be formed. An impurity of a second conductivity type is implanted into the semiconductor substrate of the integrated circuit to form a second region. The second masking layer is then removed. The integrated circuit is thermally heated to form the first and second wells in the substrate. If desired, sets of alignment keys may be formed in a semiconductor wafer by first forming a layer of insulating material over a semiconductor wafer, followed by forming a layer of masking material to define the locations of the sets of alignment keys and anisotropically etching into the semiconductor wafer to form the sets of alignment keys. The sets of alignment keys may be formed in a portion of the semiconductor wafer that is not part of a substrate for any particular integrated circuit.

摘要翻译： 提供了一种用于制造具有N型阱和P型阱的集成电路的结构和方法，其中N型阱的上表面和P型阱共面。 在集成电路上形成绝缘层。 在绝缘层上形成第一掩模层，以限定要形成的第一阱的位置。 将第一导电类型的杂质注入到集成电路的半导体衬底中以形成第一区域。 去除第一掩模层，并且在绝缘层上形成第二掩模层以限定要形成的第二阱的位置。 将第二导电类型的杂质注入到集成电路的半导体衬底中以形成第二区域。 然后去除第二掩蔽层。 集成电路被热加热以在衬底中形成第一和第二阱。 如果需要，可以在半导体晶片中形成一组对准键，首先在半导体晶片上形成绝缘材料层，然后形成掩模材料层，以限定对准键组和各向异性蚀刻的位置 半导体晶片形成一组对准键。 可以在不是用于任何特定集成电路的衬底的一部分的半导体晶片的一部分中形成对准键组。

公开(公告)号：EP0564191A2

公开(公告)日：1993-10-06

申请号：EP93302375.6

申请日：1993-03-26

申请人： SGS-THOMSON MICROELECTRONICS, INC.

发明人： Bryant, Frank R. ,  Chan, Tsui C. ,  Huang, Kuei-Wu

IPC分类号： H01L21/82 ,  H01L23/544 ,  H01L27/092 ,  H01L21/76

CPC分类号： H01L21/823892 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method is provided for fabricating an integrated circuit having an N-type well and a P-type well, with the upper surfaces of the N-type well and the P-type well coplanar. An insulating layer is formed over the integrated circuit. A first masking layer is formed over the insulating layer to define locations of a first well to be formed. An impurity of a first conductivity type is implanted into the semiconductor substrate of the integrated circuit to form a first region. The first masking layer is removed, and a second masking layer is formed over the insulating layer to define locations of a second well to be formed. An impurity of a second conductivity type is implanted into the semiconductor substrate of the integrated circuit to form a second region. The second masking layer is then removed. The integrated circuit is thermally heated to form the first and second wells in the substrate. If desired, sets of alignment keys may be formed in a semiconductor wafer by first forming a layer of insulating material over a semiconductor wafer, followed by forming a layer of masking material to define the locations of the sets of alignment keys and anisotropically etching into the semiconductor wafer to form the sets of alignment keys. The sets of alignment keys may be formed in a portion of the semiconductor wafer that is not part of a substrate for any particular integrated circuit.

摘要翻译： 提供了一种用于制造具有N型阱和P型阱的集成电路的结构和方法，其中N型阱的上表面和P型阱共面。 在集成电路上形成绝缘层。 在绝缘层上形成第一掩模层，以限定要形成的第一阱的位置。 将第一导电类型的杂质注入到集成电路的半导体衬底中以形成第一区域。 去除第一掩模层，并且在绝缘层上形成第二掩模层以限定要形成的第二阱的位置。 将第二导电类型的杂质注入到集成电路的半导体衬底中以形成第二区域。 然后去除第二掩蔽层。 集成电路被热加热以在衬底中形成第一和第二阱。 如果需要，可以在半导体晶片中形成一组对准键，首先在半导体晶片上形成绝缘材料层，然后形成掩模材料层，以限定对准键组和各向异性蚀刻的位置 半导体晶片形成一组对准键。 可以在不是用于任何特定集成电路的衬底的一部分的半导体晶片的一部分中形成对准键组。

公开(公告)号：EP0564136A1

公开(公告)日：1993-10-06

申请号：EP93302155.2

申请日：1993-03-22

申请人： SGS-THOMSON MICROELECTRONICS, INC.

发明人： Lin, Yih-Shung ,  Huang, Kuei-Wu ,  Lu, Lun-Tseng

IPC分类号： H01L21/90 ,  H01L21/3105

CPC分类号： H01L21/76819

摘要： After a first conducting layer (22) is deposited and patterned, a first insulating layer (24) is deposited over the device. A planarizing layer (26) is then deposited over the integrated circuit and etched back. Portions of the planarizing layer (26) may remain in the lower topographical regions of the first insulating layer (24) to planarize the surface of the device. A second insulating layer (28) is then deposited over the integrated circuit, followed by a third insulating layer (30). A contact via (32) is formed through the layers to expose a portion of the first conducting layer (22). A second conducting layer (34) can now be deposited and patterned on the device to make electrical contact with the first conducting layer (22).

摘要翻译： 在沉积和图案化第一导电层（22）之后，在器件上沉积第一绝缘层（24）。 然后将平坦化层（26）沉积在集成电路上并被回蚀刻。 平坦化层（26）的一部分可以保留在第一绝缘层（24）的下部拓扑区域中，以使器件的表面平坦化。 然后在集成电路上沉积第二绝缘层（28），随后沉积第三绝缘层（30）。 通过这些层形成接触通孔（32）以暴露第一导电层（22）的一部分。 现在可以在器件上沉积和图案化第二导电层（34）以与第一导电层（22）电接触。

公开(公告)号：EP0536992A2

公开(公告)日：1993-04-14

申请号：EP92309133.4

申请日：1992-10-07

申请人： SGS-THOMSON MICROELECTRONICS, INC.

发明人： Huang, Kuei-Wu

IPC分类号： H01L21/90

CPC分类号： H01L21/31056 ,  H01L21/76819

摘要： A method for planarizing an integrated circuit structure having a glass layer (15) overlying an oxide layer (13) 0f an integrated circuit is presented. The method includes the steps of selectively etching portions of the glass (15) structure that overlie portions of the oxide layer (13) that have higher elevations than other portions of the oxide layer (13), and then etching the glass layer (15) overall. The etching step includes forming a layer of photoresist (17) over the glass layer (15), exposing selected areas (20) of the photoresist (17) over the portions of the oxide layer (13) that have higher elevations than other portions of the oxide layer (13), removing the exposed areas of the photoresist (17), and etching the glass layer (15) within the removed areas of the photoresist. The mask used in patterning the photoresist can be the same mask, or its negative, that is used in forming the metalization layer (11) over which the oxide (13) and glass layers (15) have been formed.
Additionally, an integrated circuit structure is presented that includes a substrate (10) in which integrated circuit elements are constructed, a first interconnection metalization (11) over the substrate (10) interconnecting selected ones of the integrated circuit elements, and an oxide layer (13) over the substrate (10) and the first metal interconnection pattern (11). A glass layer (15) over the oxide layer (13) is substantially planar between portions that overlie the metalization (11) and portions that do not over lie the metalization (11).

摘要翻译： 提出了一种用于平面化集成电路结构的方法，该集成电路结构具有覆盖在集成电路上的氧化物层（13）上的玻璃层（15）。 该方法包括以下步骤：选择性地蚀刻玻璃（15）结构的部分，其覆盖氧化物层（13）的比氧化物层（13）的其它部分高的高度的部分，然后蚀刻玻璃层（15） 总体。 蚀刻步骤包括在玻璃层（15）上形成光致抗蚀剂层（17），将光致抗蚀剂（17）的选定区域（20）暴露在氧化物层（13）的比其它部分高的部分上 氧化物层（13），去除光致抗蚀剂（17）的暴露区域，以及蚀刻去除的光致抗蚀剂区域内的玻璃层（15）。 用于图案化光致抗蚀剂的掩模可以是与形成氧化物（13）和玻璃层（15）一起形成的金属化层（11）中使用的掩模或其负极。 此外，提出了一种集成电路结构，其包括其中构成集成电路元件的衬底（10），在互连所选择的集成电路元件的衬底（10）上方的第一互连金属化（11）和氧化物层 13）在基板（10）和第一金属互连图案（11）之上。 在氧化物层（13）之上的玻璃层（15）在金属化层（11）的上部和不在金属化层（11）之上的部分之间基本上是平面的。