公开(公告)号：EP3262688A1

公开(公告)日：2018-01-03

申请号：EP16722739.6

申请日：2016-04-20

申请人： SanDisk Technologies LLC

发明人： NISHIKAWA, Masatoshi ,  INOUE, Akira ,  TOYAMA, Fumiaki

IPC分类号： H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/115

CPC分类号： H01L29/7834 ,  H01L21/26513 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/11293 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66598

摘要： A field effect transistor having a higher breakdown voltage can be provided by forming a contiguous dielectric material layer over gate stacks, forming via cavities laterally spaced from the gate stacks, selectively depositing a single crystalline semiconductor material, and converting upper portions of the deposited single crystalline semiconductor material into elevated source/drain regions. Lower portions of the selectively deposited single crystalline semiconductor material in the via cavities can have a doping of a lesser concentration, thereby effectively increasing the distance between two steep junctions at edges of a source region and a drain region. Optionally, embedded active regions for additional devices can be formed prior to formation of the contiguous dielectric material layer. Raised active regions contacting a top surface of a substrate can be formed simultaneously with formation of the elevated active regions that are vertically spaced from the top surface.

公开(公告)号：EP1550154B1

公开(公告)日：2015-02-18

申请号：EP03750362.0

申请日：2003-09-19

申请人： Infineon Technologies AG

发明人： HOLZ, Jürgen ,  SCHRÜFER, Klaus ,  TEWS, Helmut

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/66636 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/3205 ,  H01L29/0653 ,  H01L29/41783

公开(公告)号：EP1579488B1

公开(公告)日：2011-12-07

申请号：EP03813688.3

申请日：2003-12-15

申请人： NXP B.V. ,  IMEC

发明人： VENEZIA, Vincent, C. ,  DACHS, Charles, J., J. ,  HOOKER, Jacob, C. ,  VAN DAL, Marcus, J., H.

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/285

CPC分类号： H01L29/41783 ,  H01L21/26586 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/1045 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  Y10T307/74

摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a field effect transistor, in which method a semiconductor body (1) of a semiconductor material is provided, at a surface thereof, with a source region (2) and a drain region (3) and with a gate region (4) between the source region (2) and the drain region (3), which gate region comprises a semiconductor region (4A) of a further semiconductor material that is separated from the surface of the semiconductor body (1) by a gate dielectric (5), and with spacers (6) adjacent to the gate region (4), for forming the source and drain regions (2,3), in which method the source region (2) and the drain region (3) are provided with a metal layer (7) which is used to form a compound (8) of the metal and the semiconductor material, and the gate region (4) is provided with a metal layer (7) which is used to form a compound (8) of the metal and the further semiconductor material. The known method in which different metal layers are used to silicidate source and drain regions and gate regions (2,3,4) has several drawbacks. A method according to the invention is characterized in that before the spacers (6) are formed, a sacrificial region (4B) of a material that may be selectively etched with respect to the semiconductor region (4A) is deposited on top of the semiconductor region (4A), and after the spacers (6) have been formed, the sacrificial layer (4B) is removed by etching, and after removal of the sacrificial layer (4B), a single metal layer (7) is deposited contacting the source, drain and gate regions (2,3,4). This method is on the one hand very simple as it requires only a single metal layer and few, straight-forward steps and it is compatible with existing (silicon) technology, and on the other hand it results in a (MOS)FET which does not suffer from a depletion layer effect in the fully silicided gate (4).

摘要翻译： 本发明涉及一种制造具有场效应晶体管的半导体器件（10）的方法，在该方法中，半导体材料的半导体本体（1）在其表面处设置有源极区（2）和 漏极区域（3）以及源极区域（2）和漏极区域（3）之间的栅极区域（4），该栅极区域包括另一半导体材料的半导体区域（4A） 半导体本体（1）通过栅极电介质（5）以及与栅极区域（4）相邻的用于形成源极区域和漏极区域（2,3）的间隔物（6），在该方法中，源极区域 ）和漏极区（3）设置有用于形成金属和半导体材料的化合物（8）的金属层（7），并且栅极区（4）设置有金属层（7） ），其用于形成金属和另外的半导体材料的化合物（8）。 其中使用不同金属层来硅化源极区和漏极区以及栅极区（2,3,4）的已知方法具有若干缺点。 根据本发明的方法的特征在于，在形成间隔物（6）之前，可以将相对于半导体区域（4A）选择性蚀刻的材料的牺牲区域（4B）沉积在半导体区域 （4A）中，并且在已经形成隔离物（6）之后，通过蚀刻去除牺牲层（4B），并且在去除牺牲层（4B）之后，沉积与源极接触的单个金属层（7） 漏极和栅极区域（2,3,4）。 这种方法一方面非常简单，因为它只需要一个金属层和很少的直接步骤，并且与现有的（硅）技术兼容，另一方面它产生了一个（MOS）FET，其 不会在完全硅化的栅极（4）中遭受耗尽层效应。

公开(公告)号：EP2171749A4

公开(公告)日：2011-11-16

申请号：EP08770801

申请日：2008-06-12

申请人： FREESCALE SEMICONDUCTOR INC

发明人： ZHANG DA ,  FOISY MARK C

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/41783 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

公开(公告)号：EP2191505A1

公开(公告)日：2010-06-02

申请号：EP08807491.9

申请日：2008-08-29

申请人： NXP B.V.

发明人： MEUNIER-BEILLARD, Philippe ,  HERINGA, Anco ,  DONKERS, Johannes

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/41775 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/7833 ,  Y10S257/90

摘要： A method of manufacturing a transistor (300), the method comprising forming a gate (101) on a substrate (102), forming a spacer (201) on lateral side walls of the gate (101) and on an adjacent portion (202) of the substrate (102), modifying material of the spacer (201) so that the modified spacer (301) covers only a lower portion (303) of the lateral side walls of the gate (101), and providing source/drain regions (301) in the modified spacer (301).

摘要翻译： 一种制造晶体管（300）的方法，该方法包括在衬底（102）上形成栅极（101），在栅极（101）的侧壁上和相邻部分（202）上形成间隔物（201） （101）的横向侧壁的下部（303），并且提供源极/漏极区（201），改变间隔物（201）的材料，使得改性的间隔物（301）仅覆盖栅极 301）在修改的间隔物（301）中。

公开(公告)号：EP2171749A1

公开(公告)日：2010-04-07

申请号：EP08770801.2

申请日：2008-06-12

申请人： Freescale Semiconductor, Inc.

发明人： ZHANG, Da ,  FOISY, Mark C.

IPC分类号： H01L21/265

CPC分类号： H01L29/41783 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A transistor is formed by providing a semiconductor layer (103) and forming a control electrode (105) overlying the semiconductor layer. A portion of the semiconductor layer is removed lateral to the control electrode to form a first recess (201) and a second recess (203) on opposing sides of the control electrode. A first stressor (301) is formed within the first recess and has a first doping profile. A second stressor (303) is formed within the second recess and has the first doping profile. A third stressor (401) is formed overlying the first stressor. The third stressor has a second doping profile that has a higher electrode current doping concentration than the first profile. A fourth stressor (403) overlying the second stressor is formed and has the second doping profile. A first current electrode and a second current electrode of the transistor include at least a portion of the third stressor and the fourth stressor, respectively.

公开(公告)号：EP2120258A1

公开(公告)日：2009-11-18

申请号：EP09159902.7

申请日：2009-05-11

申请人： Commissariat à l'Energie Atomique

发明人： Vinet, Maud ,  Poiroux, Thierry ,  Previtali, Bernard

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/78 ,  H01L29/786 ,  H01L29/51

CPC分类号： H01L29/41783 ,  H01L21/823814 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/66772 ,  H01L29/7834 ,  H01L29/7839 ,  H01L29/78648

摘要： Procédé de réalisation d'un transistor (100) à effet de champ, comportant :
a) la réalisation, sur un substrat (108, 110), d'une structure comprenant un canal (102), une grille (114) et un masque dur (118),
b) formation d'un diélectrique recouvrant complètement ladite structure et des emplacements d'une source (136) et d'un drain (138) du transistor et une zone périphérique,
c) réalisation, dans la portion diélectrique, de deux trous (128) mettant à nu des flancs latéraux du canal,
d) dépôt d'une première couche métallique (132) sur les parois des trous,
e) siliciuration desdits flancs latéraux ;
f) dépôt d'une seconde couche métallique sur la première couche métallique, formant, avec les portions précédemment siliciurées, la source (136) et le drain (138) du transistor,
g) planarisation mécano-chimique de la seconde couche métallique avec arrêt sur le masque dur.

摘要翻译： 该方法包括沉积一个金属层（132），其覆盖孔的侧壁上的通道侧壁，并使侧面硅化。 形成具有硅酸化部分侧面的MOS晶体管（100）的源极和漏极的另一金属层沉积在层（132）上。 后一层在硬掩模（118）上用停止机械化学平面化。 在层（132）沉积之后，在层（132）上沉积钛，氮化钛或钨基层。 在沉积后一层之后，在后一层上沉积氧化物层。

公开(公告)号：EP1642331A1

公开(公告)日：2006-04-05

申请号：EP04741717.5

申请日：2004-06-02

申请人： Infineon Technologies AG

发明人： HOFMANN, Franz ,  LUYKEN, Richard Johannes ,  RÖSNER, Wolfgang ,  SPECHT, Michael

IPC分类号： H01L21/60

CPC分类号： H01L29/41783 ,  H01L21/28518 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/78 ,  Y10S438/964

摘要： A contact resistance may be significantly reduced, whereby a semi-conducting material layer (84) is deposited on a substrate in the contact region and a metallic or metal-comprising layer (102) is deposited thereon, such that in a transition region (210), parts of the semiconducting material layer (84) are multiply penetrated by parts of the layer (102).

公开(公告)号：EP0785573B1

公开(公告)日：2005-12-14

申请号：EP97200810.6

申请日：1995-10-27

申请人： STMicroelectronics, Inc.

发明人： Chan, Tsiu Chiu ,  Smith, Gregory C.

IPC分类号： H01L21/336 ,  H01L21/60

CPC分类号： H01L29/0847 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833

摘要： A method is provided for forming a planar transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A transistor encapsulated in a dielectric is formed over a substrate. First source and drain regions are formed in the substrate adjacent the transistor. Metal raised second source and drain regions are formed which overly exposed portions of the first substrate source and drain regions adjacent the transistor. The raised second source and drain regions are formed such that an upper surface of the raised second source and drain regions are substantially planar with an upper surface of the transistor. The dielectric encapsulating the transistor electrically isolates the transistor from the raised second source and drain regions.

公开(公告)号：EP1550154A1

公开(公告)日：2005-07-06

申请号：EP03750362.0

申请日：2003-09-19

申请人： Infineon Technologies AG

发明人： HOLZ, Jürgen ,  SCHRÜFER, Klaus ,  TEWS, Helmut

IPC分类号： H01L21/336 ,  H01L29/06

CPC分类号： H01L29/66636 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/3205 ,  H01L29/0653 ,  H01L29/41783

摘要： The invention relates to a field effect transistor with local source/drain insulation and to an associated method of production. An interspaced source recess (SV) and a drain recess (DV) are created in a semiconductor substrate (1) and a recess insulating layer (VI) is formed at least in a bottom area of the source and drain recess (SV, DV) and an electric conducting filling layer (F) is placed in said source and drain recesses (SV, DV) in order to create source and drain areas (S, D). A field effect transistor is thus provided, exhibiting reduced junction capacities, together with a gate dielectric (3) and a gate layer (4).