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20 条记录 (耗时 0.012 秒)

    Method for forming a metal contact
    3.
    发明公开
    Method for forming a metal contact 失效
    Verfahren zum Herstellen eines Metallkontaktes。

    公开(公告)号：EP0485130A2

    公开(公告)日：1992-05-13

    申请号：EP91310146.5

    申请日：1991-11-01

    申请人： SGS-THOMSON MICROELECTRONICS, INC. (a Delaware corp.)

    发明人： Chen, Fusen E. ,  Liou, Fu-Tai ,  Lin, Yih-Shung ,  Dixit, Girish A. ,  Wei, Che-Chia

    IPC分类号： H01L21/285 ,  H01L21/3205 ,  H01L21/90

    CPC分类号： H01L21/76843 ,  C23C16/0281 ,  C23C16/20 ,  H01L21/28512 ,  H01L21/32051 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is provided for depositing aluminum thin film layers to form improved quality contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.

    摘要翻译： 提供一种用于沉积铝薄膜层以在半导体集成电路器件中形成改进的质量接触的方法。 所有或一些沉积过程在允许改善沉积的铝原子的表面迁移的温度下以相对低的沉积速率进行。 在这些条件下沉积的铝倾向于填充接触孔而不形成空隙。 低温沉积步骤可以通过沉积铝来开始，而包含集成电路器件的晶片正在沉积室内的较冷的温度被加热。

    Local interconnect for integrated circuits
    4.
    发明公开
    Local interconnect for integrated circuits 失效
    Lokalverbindungenfürintegrierte Schaltungen。

    公开(公告)号：EP0400821A2

    公开(公告)日：1990-12-05

    申请号：EP90304926.0

    申请日：1990-05-08

    申请人： SGS-THOMSON MICROELECTRONICS, INC.

    发明人： Liou, Fu-Tai ,  Lin, Yih-Shung ,  Chen, Fusen E.

    IPC分类号： H01L29/62 ,  H01L21/60

    CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L21/32155 ,  H01L21/76895 ,  H01L23/53271 ,  H01L29/78 ,  H01L2924/0002 ,  Y10S148/015 ,  Y10S148/019 ,  Y10S148/02 ,  H01L2924/00

    摘要： A silicide layer, to improve conductivity, is formed over a first layer of polycrystalline silicon, followed by a second layer of polycrystalline silicon. This structure is then patterned to form gate regions over active areas. A layer of metal silicide is formed over the entire surface of the chip, and patterned to form local interconnect. Etching of the second metal silicide layer is stopped by the second polycrystalline silicon layer, thereby protecting the first metal silicide layer from damage.

    摘要翻译： 在第一层多晶硅上形成硅化物层，以提高导电性，随后是第二层多晶硅。 然后将该结构图案化以在有效区域上形成栅极区域。 在芯片的整个表面上形成金属硅化物层，并且被图案化以形成局部互连。 通过第二多晶硅层阻止第二金属硅化物层的蚀刻，从而保护第一金属硅化物层免受损坏。

    Integrated circuit with planarized dielectric layer between successive polysilicon layers
    5.
    发明公开
    Integrated circuit with planarized dielectric layer between successive polysilicon layers 失效
    具有连续的多晶硅层之间的平面化电介质层的集成电路

    公开(公告)号：EP0769813A3

    公开(公告)日：1998-04-08

    申请号：EP96307356.4

    申请日：1996-10-09

    申请人： SGS-THOMSON MICROELECTRONICS, INC.

    发明人： Lin, Yih-Shung

    IPC分类号： H01L21/768

    CPC分类号： H01L21/768

    摘要： A method of forming a portion of a semiconductor integrated circuit having a semiconductor substrate as well as the resulting integrated circuit. In the inventive method, various steps are involved. In one embodiment, for example, the method steps are as follows. First, there is formed a first polysilicon layer overlying and in contact with the semiconductor substrate. Second, a plurality of conductive members are patterned from the first polysilicon layer. Third, there is formed a dielectric layer having an upper planar surface and having a lower surface contacting the semiconductor substrate and the plurality of conductive members from the first polysilicon layer. Fourth, there is formed a second polysilicon layer overlying and in contact with the dielectric layer. Fifth, a plurality of conductive members are formed from the second polysilicon layer. Lastly, there is formed a metallic layer over the plurality of conductive members from the second polysilicon layer.