摘要:
A power CMOS operational amplifier with a differential output (Vout-,Vout+), having an intrinsically stable current absorption under rest conditions, comprises two symmetric branches, each comprising a first folded cascode input inverting stage (M1-M10), a level shifting circuit (M11,M12), a second current mirror type noninverting amplifying stage (M13-M18) and a third output inverting stage (M19,M20), constituted by a complementary pair of transistors, connected in a common source configuration between the supply rails and driven by the output (A",B") of the second noninverting stage and by the output (A',B') of the level shifting circuit. Frequency compensation is accomplished by means of two capacitors (Cc1,Cc2) connected between each of the two output terminals (Vout-,Vout+) of the amplifier and the output (A,B) of the first inverting stage (M1-M10) and a node of the output branch of the noninverting current mirror stage (M13-M18). A single common mode feedback network (McM1-McM3) stabilizes both symmetric branches of the amplifier.
摘要:
The antibounce circuit comprises: a) a first flip-flop constituted by a first and a second NAND gate (10, 12) having their respective outputs connected to one of the inputs of the other gate, the free input of the first gate being the input for said digital signal; b) a second flip-flop constituted by a third and a fourth NAND gate (14, 16) having their respective outputs connected to one of the inputs of the other gate, the free input of the third gate being connected to the output of the first gate; c)a non-inverting delay circuit (20, 22, 24) connecting the output of the third gate to the free input of the second gate; d) a first inverter connecting the output of the delay circuit to the free input of the fourth gate.
摘要:
A CMOS power operational amplifier with large output voltage swing and high noise rejection is obtained by coupling a folded cascode type differential input stage and an output stage comprising an intermediate signal shifting amplifier and two common source output stages. Constant current generators inject into the drain of grounded gate MOS transistors pairs of said folded cascode type stage and of said intermediately signal shifting amplifier, respectively, a current which is pulled out of the source of the same grounded gate transistors by other constant current generators for increasing the effective transconductance of said grounded gate transistors pairs.
摘要:
A CMOS power operational amplifier with large output voltage swing and high noise rejection is obtained by coupling a folded cascode type differential input stage and an output stage comprising an intermediate signal shifting amplifier and two common source output stages. Constant current generators inject into the drain of grounded gate MOS transistors pairs of said folded cascode type stage and of said intermediately signal shifting amplifier, respectively, a current which is pulled out of the source of the same grounded gate transistors by other constant current generators for increasing the effective transconductance of said grounded gate transistors pairs.
摘要:
The amplifier includes a pair of bipolar input transistors (Q1, Q2), each having a base adapted to receive a differential input signal, a collector and an emitter which is biased by a first fixed current source (M7, M8) of its own and a degeneration resistor (R) which connects the emitters of the two bipolar transistors. The collector of each bipolar transistor is also biased by a second fixed current source (M5, M6) with a smaller current than that of the first source, and the collectors of the two bipolar transistors are furthermore connected to the input terminals of respective MOS amplifier devices (M1, M2, M3, M4, R L ). The amplifier can be made in BCD, BiCMOS or purely CMOS technology, in which case the bipolar transistors are obtained as lateral bipolar transistors.
摘要:
The amplifier includes a pair of bipolar input transistors (Q1, Q2), each having a base adapted to receive a differential input signal, a collector and an emitter which is biased by a first fixed current source (M7, M8) of its own and a degeneration resistor (R) which connects the emitters of the two bipolar transistors. The collector of each bipolar transistor is also biased by a second fixed current source (M5, M6) with a smaller current than that of the first source, and the collectors of the two bipolar transistors are furthermore connected to the input terminals of respective MOS amplifier devices (M1, M2, M3, M4, R L ). The amplifier can be made in BCD, BiCMOS or purely CMOS technology, in which case the bipolar transistors are obtained as lateral bipolar transistors.