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29 条记录 (耗时 0.012 秒)

    Low-resistance salicide fill for trench capacitors
    1.
    发明公开
    Low-resistance salicide fill for trench capacitors 有权
    Salizidfüllungmit niedrigem WiderstandfürGrabenkondensatoren

    公开(公告)号：EP0967643A3

    公开(公告)日：2003-08-20

    申请号：EP99304729.9

    申请日：1999-06-17

    申请人： International Business Machines Corporation ,  SIEMENS AKTIENGESELLSCHAFT

    发明人： Gambino, Jeffrey P. ,  Gruening, Ulrike ,  Mandelman, Jack A. ,  Radens, Carl J.

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10861

    摘要： Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide (32) as a component of the trench electrode (26,32,34) in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell leats and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.

    摘要翻译： 使用导致难熔金属硅化物作为沟槽的下部区域中的沟槽电极的部件的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含有自对接硅化物的沟槽电极显示出降低的串联电阻，从而能够减少接地规则存储器单元格和/或减少的单元访问时间。 本发明的沟槽电容器特别可用作DRAM存储单元的组件。

    Method of connecting a dram trench capacitor
    6.
    发明公开
    Method of connecting a dram trench capacitor 失效
    KontaktierverfahrenfürDRAM-Grabenkondensator

    公开(公告)号：EP0791959A1

    公开(公告)日：1997-08-27

    申请号：EP97102361.9

    申请日：1997-02-13

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Stengl, Reinhard J. ,  Hammerl, Erwin ,  Mandelman, Jack A. ,  Ho, Herbert L. ,  Srinivasan, Radhika ,  Short, Alvin P.

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10861 ,  H01L27/10832

    摘要： In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection (90) is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material (60) which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

    摘要翻译： 在用于在DRAM单元中的沟槽存储电容器和存取晶体管之间进行电连接的方法中，电连接（90）通过有选择地控制在沟槽中存在的N型或P型掺杂剂的扩散扩散形成 通过从沟槽侧壁外延（epi）生长的单晶半导体材料（60）。 这种外延生长的单晶层作为在常规DRAM的处理中可能发生的过量掺杂剂扩散扩散的障碍。

    Low-resistance salicide fill for trench capacitors
    8.
    发明公开
    Low-resistance salicide fill for trench capacitors 有权
    Verfahren zurSalizidfüllungmit Niedrigem WiderstandfürGrabenkondensatoren

    公开(公告)号：EP0967643A2

    公开(公告)日：1999-12-29

    申请号：EP99304729.9

    申请日：1999-06-17

    申请人： International Business Machines Corporation ,  SIEMENS AKTIENGESELLSCHAFT

    发明人： Gambino, Jeffrey P. ,  Gruening, Ulrike ,  Mandelman, Jack A. ,  Radens, Carl J.

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10861

    摘要： Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide as a component of the trench electrode in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell leats and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.

    摘要翻译： 使用导致难熔金属硅化物作为沟槽的下部区域中的沟槽电极的部件的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含有自对接硅化物的沟槽电极显示出降低的串联电阻，从而能够减少接地规则存储器单元格和/或减少的单元访问时间。 本发明的沟槽电容器特别可用作DRAM存储单元的组件。

    Method for forming a buried strap by controlled recrystallisation, in a semiconductor memory device, and semiconductor memory device thereby formed
    10.
    发明公开
    Method for forming a buried strap by controlled recrystallisation, in a semiconductor memory device, and semiconductor memory device thereby formed 失效
    一种用于生产通过受控再结晶在由此制造的半导体存储器件和半导体存储器件的掩埋连接处理

    公开(公告)号：EP0739033A2

    公开(公告)日：1996-10-23

    申请号：EP96105064.8

    申请日：1996-03-29

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  SIEMENS AKTIENGESELLSCHAFT ,  KABUSHIKI KAISHA TOSHIBA

    发明人： Hammerl, Erwin ,  Mandelman, Jack A. ,  Ho, Herbert L. ,  Shiozawa, Junichi ,  Stengl, Reinhard Johannes

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/74 ,  H01L21/225

    CPC分类号： H01L27/10861

    摘要： A method of forming a coupled capacitor and transistor is provided. A trench is formed in a semiconductor substrate (10) and an impurity-doped first conductive region (105) is then formed by filing the trench with an impurity-doped first conductive material. The impurity-doped first conductive region (105) is etched back to a first level within the trench. An insulating layer (106) is then formed on a sidewall of the portion of the trench (103) opened by the etching back of the impurity-doped first conductive region and a second conductive region (107) is formed by filing the remainder of the trench with a second conductive material. The insulating layer (106) and the second conductive region (107) are etched back to a second level within the trench and an amorphous silicon layer (108) is formed in the portion of the trench opened by the etching back of the insulating layer (106) and the second conductive region (107). The undoped amorphous silicon layer (108) is etched back to a third level within the trench. The undoped amorphous silicon layer (108) is then recrystallized. Impurities are outdiffused from the impurity-doped first conductive region to the semiconductor substrate through the recrystallized silicon layer. A source/drain region of the transistor is formed adjacent to an intersection of the trench and the surface of the semiconductor substrate. The outdiffused impurities and the recrystallized silicon layer constitute a buried strap (126) for electrically connecting the first and second conductive layers in the trench to the source/drain region.

    摘要翻译： 形成耦合电容器和晶体管包括：（a）形成在半导体衬底的沟槽; （B）通过填充在掺杂有杂质的第一导电材料的沟槽中形成掺杂有杂质的第一导电区域的; （C）回蚀刻掺杂有杂质的第一导电区域，以在所述沟槽内的第一电平; （D）上形成由所述回蚀刻开设沟槽的部分的侧壁绝缘层; （E）通过填充有第二导电材料的沟槽的剩余部分形成第二导电区域; （F）回蚀刻绝缘层和第二导电材料，以在所述沟槽内的第二电平; （G）在由所述绝缘层和所述第二导电区域的蚀刻开设背面沟槽的部分未掺杂非晶硅层的形成; （H）回蚀刻未掺杂的无定形硅层，以在沟槽内的第三电平; （I）重结晶所述非晶硅层; （J）扩散出从杂质掺杂第一导电区域通过重结晶Si层的半导体衬底的杂质; （K）形成源极/在所述沟槽和所述底物的表面的交叉点漏毗邻晶体管的区域中，扩散出来的杂质和构成隐埋条用于电重结晶Si层连接在所述第一和第二导电层 沟槽到源极/漏极区域。