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公开(公告)号：EP0967644A3
公开(公告)日：2003-07-02
申请号：EP99304812.3
申请日：1999-06-18
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861 , H01L29/945
摘要： A bottle-shaped trench capacitor (310) having an expanded lower trench portion with an epi layer (365) therein. The epi layer serves as the buried plate of the trench capacitor. A diffusion region (367) surrounds the expanded lower trench portion to enhance the dopant concentration of the epi layer. The diffusion region is formed by, for example, gas phase doping, plasma doping, or plasma immersion ion implantation.
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公开(公告)号：EP0967653A2
公开(公告)日：1999-12-29
申请号：EP99304810.7
申请日：1999-06-18
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10861 , H01L29/945
摘要： A trench capacitor with an epi layer in the lower portion of the trench. The epi layer serves as the buried plate of the trench capacitor. A diffusion region surrounds the lower portion of the trench to enhance the dopant concentration of the epi layer. The diffusion region is formed by, for example, gas phase doping, plasma doping, or plasma immersion ion implantation.
摘要翻译： 在沟槽的下部具有外延层的沟槽电容器。 外延层用作沟槽电容器的掩埋板。 扩散区域围绕沟槽的下部以增强外延层的掺杂剂浓度。 扩散区通过例如气相掺杂，等离子体掺杂或等离子体浸入离子注入形成。
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公开(公告)号：EP0967653A3
公开(公告)日：2003-07-02
申请号：EP99304810.7
申请日：1999-06-18
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10861 , H01L29/945
摘要： A trench capacitor with an epi layer (365) in the lower portion of the trench. The epi layer serves as the buried plate of the trench capacitor. A diffusion region (367) surrounds the lower portion of the trench to enhance the dopant concentration of the epi layer. The diffusion region is formed by, for example, gas phase doping, plasma doping, or plasma immersion ion implantation.
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公开(公告)号：EP0967644A2
公开(公告)日：1999-12-29
申请号：EP99304812.3
申请日：1999-06-18
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861 , H01L29/945
摘要： A bottle-shaped trench capacitor having an expanded lower trench portion with an epi layer therein. The epi layer serves as the buried plate of the trench capacitor. A diffusion region surrounds the expanded lower trench portion to enhance the dopant concentration of the epi layer. The diffusion region is formed by, for example, gas phase doping, plasma doping, or plasma immersion ion implantation.
摘要翻译： 一种瓶形沟槽电容器，其具有在其中具有外延层的扩展的下沟槽部分。 外延层用作沟槽电容器的掩埋板。 扩散区围绕扩展的下沟槽部分以增强外延层的掺杂剂浓度。 扩散区通过例如气相掺杂，等离子体掺杂或等离子体浸入离子注入形成。
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5.发明公开Trench capacitor with epitaxial buried layer 审中-公开Grabenkondensator mit epitaktischer vergrabener Schicht
公开(公告)号：EP0949684A3
公开(公告)日：2000-04-05
申请号：EP99106682.0
申请日：1999-04-01
发明人： Schrems, Martin
IPC分类号： H01L29/94
CPC分类号： H01L27/10861 , H01L29/945
摘要： A trench capacitor (310) with an epitaxial layer (365) in the lower portion of the trench. The epitaxial layer (365) may be doped to serve as a buried plate.
摘要翻译： 沟槽电容器，其在沟槽的下部具有外延层。 外延层可以被掺杂以用作掩埋板。
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公开(公告)号：EP0905760A3
公开(公告)日：2001-10-24
申请号：EP98117728.0
申请日：1998-09-18
发明人： Schrems, Martin
IPC分类号： H01L21/334 , H01L29/94 , H01L21/8242
CPC分类号： H01L27/10861 , H01L29/66181 , H01L29/94 , H01L29/945
摘要： The method includes providing a semiconductor; forming a non-uniform layer (22) on a surface of the semiconductor (10); subjecting the semiconductor and the non-uniform layer thereon to heat and pressure producing pits (25) in a surface of the semiconductor (10); forming a dielectric (32) over the pitted surface of the semiconductor to provide the dielectric (32) for the capacitor(35). The step of subjecting the semiconductor to heat and pressure producing pits (25) in a surface of the semiconductor comprises the step of subjecting the semiconductor with the dielectric layer thereon to a first anneal and wherein the step of rounding the pits (25') produced in the surface of the semiconductor comprises the step of subjecting the semiconductor to a second anneal. A DRAM cell (40) is provided having a single crystal body. The body has formed therein a transistor (42) and a capacitor (35) coupled to the transistor (42). The capacitor includes a doped single crystal semiconductor portion (27) formed in the body (10), such portion having a pitted surface. The doped semiconductor portion (27) provides a first electrode for the capacitor (35). A dielectric (32) is disposed over the pitted surface of the semiconductor. A second electrode (37) for the capacitor (35) is disposed over the dielectric and electrically is connected to the transistor (42).
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7.发明公开Combined preanneal/oxidation step using rapid thermal processing (RTP) 审中-公开采用快速热处理（RTP）结合的preanneal /氧化步骤
公开(公告)号：EP0984486A2
公开(公告)日：2000-03-08
申请号：EP99115879.1
申请日：1999-08-12
IPC分类号： H01L21/316
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/31662
摘要： A combined preanneal/oxidation step using a rapid thermal process (RTP) for treatment of a silicon wafer to form a thermal oxide of a given thickness while simultaneously adjusting the denuded zone depth and bulk micro defect density (BMD) comprising: exposing the wafer to a controlled temperature and a controlled preannealing time in an oxidation ambient at ambient pressure to obtain a target thermal oxide thickness that is preselected to correspond to a preselected denuded zone depth.
摘要翻译： 使用快速热处理（RTP）的组合预氧化/氧化步骤来处理硅晶片以形成给定厚度的热氧化物，同时调整裸露区深度和体微缺陷密度（BMD），包括：将晶片暴露于 在环境压力下的氧化环境中的受控温度和受控的预退火时间，以获得预选对应于预先选定的露出区深度的目标热氧化物厚度。
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公开(公告)号：EP0971414A1
公开(公告)日：2000-01-12
申请号：EP98110933.3
申请日：1998-06-15
发明人： Schrems, Martin , Morhard, Klaus-Dieter , Wurster, Kai , Lamprecht, Alexandra , Faul, Jürgen , Dequiedt, Odile
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10861 , H01L27/10829
摘要： Die vorliegende Erfindung schafft einen Grabenkondensator, insbesondere zur Verwendung in einer Halbleiter-Speicherzelle (100), mit einem Isolationskragen (168) mit einem Graben (108), der in einem Substrat (101) gebildet ist; dem Isolationskragen (168), der im oberen Bereich des Grabens (108) gebildet ist; einer optionellen vergrabenen Platte (165) im Substratbereich in der Umgebung des unteren Bereichs des Grabens (108) als erste Kondensatorplatte; einer dielektrischen Schicht (164) zur Verkleidung des unteren Bereichs des Grabens (108) und des Isolationskragens (168) als Kondensatordielektrikum; einem in den Graben (108) gefüllten leitenden zweiten Füllmaterial (161) als zweite Kondensatorplatte und einem vergrabenen Kontakt unterhalb der Oberfläche des Substrats (101); wobei das Substrat (101) unterhalb seiner Oberfläche im Bereich des vergrabenen Kontakts einen durch Implantation, Plasmadotierung und/oder Gasphasenabscheidung eingebrachten Dotierbereich (250; 250') aufweist. Vorzugsweise wird an der Grenzfläche (201) des vergrabenen Kontakts eine Tunnelschicht, insbesondere eine Oxid-, Nitrid- oder Oxinitridschicht, gebildet.
摘要翻译： 在其表面下方，在掩埋接触区域中，衬底（101）具有通过注入，等离子体掺杂和/或气相沉淀工艺产生的掺杂区（250）。 具有绝缘套环和埋入触点的凹坑电容器，用于半导体存储单元（100），用于产生掺杂区域。
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9.发明公开
公开(公告)号：EP0984486A3
公开(公告)日：2000-04-19
申请号：EP99115879.1
申请日：1999-08-12
IPC分类号： H01L21/316 , H01L21/322
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/31662
摘要： A combined preanneal/oxidation step using a rapid thermal process (RTP) for treatment of a silicon wafer to form a thermal oxide of a given thickness while simultaneously adjusting the denuded zone depth and bulk micro defect density (BMD) comprising: exposing the wafer to a controlled temperature and a controlled preannealing time in an oxidation ambient at ambient pressure to obtain a target thermal oxide thickness that is preselected to correspond to a preselected denuded zone depth.
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公开(公告)号：EP0967646A3
公开(公告)日：2000-03-29
申请号：EP99111309.3
申请日：1999-06-10
IPC分类号： H01L23/00
CPC分类号： H01L27/10861 , H01L21/3003 , H01L29/66181 , H01L2924/0002 , Y10S438/918 , H01L2924/00
摘要： A method for reducing a capacitance formed on a silicon substrate. The capacitance has, as a dielectric material thereof, a silicon dioxide layer on a surface of the silicon substrate. The method includes the step of introducing hydrogen atoms into a portion of said surface to increase the dielectric constant of such portion of the surface increasing the effective thickness of the dielectric material and hence reducing said capacitance. The method including the step of forming the silicon dioxide layer with a thickness greater than two nanometers. The step of introducing hydrogen comprises the step of forming hydrogen atoms in the surface with concentrations of 10 17 atoms per cubic centimeter, or greater. In one embodiment the hydrogen atoms are formed by baking in hydrogen at a temperature of 950°C to 1100°C and pressure greater than 100 Torr. A trench capacitor DRAM cell is provided wherein the hydrogen provides a passivation layer to increase the effective capacitance around a collar region and thereby reduce unwanted transistor action.
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