公开(公告)号：EP2888759A4

公开(公告)日：2016-04-13

申请号：EP13831713

申请日：2013-07-29

申请人： SILICON STORAGE TECH INC

发明人： LIU XIAN ,  TADAYONI MANDANA ,  SU CHIEN-SHENG ,  DO NHAN

IPC分类号： H01L21/336 ,  H01L21/265 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/26586 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

摘要： A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees.

公开(公告)号：EP2823506A4

公开(公告)日：2015-11-04

申请号：EP13757434

申请日：2013-02-01

申请人： SILICON STORAGE TECH INC

发明人： TOREN WILLEM-JAN ,  LIU XIAN ,  METZGER-BRUECKL GERHARD ,  DO NHAN ,  WEGE STEPHAN ,  MIRIDI NADIA ,  SU CHIEN-SHENG ,  BERNARDI CECILE ,  CUEVAS LIZ ,  GUYOT FLORENCE ,  CHEN YUEH-HSIN ,  OM MANI HENRY ,  TADAYONI MANDANA

IPC分类号： H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76283 ,  H01L27/11521 ,  H01L27/11568

摘要： A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.

摘要翻译： 用于非易失性存储器阵列的堆叠栅极结构具有半导体衬底，该半导体衬底具有多个基本上平行的间隔开的有源区，每个有源区具有沿第一方向的轴。 第一绝缘材料在垂直于第一方向的第二方向上位于每个堆叠栅极结构之间。 每个堆叠栅极结构在有源区上具有第二绝缘材料，在第二绝缘材料上方具有电荷保持栅极，在电荷保持栅极上方具有第三绝缘材料，以及在第三绝缘材料上的控制栅极的第一部分。 控制栅极的第二部分在控制栅极的第一部分之上，并且在与其相邻并在第二方向上延伸的第一绝缘材料之上。 第四绝缘材料位于控制栅极的第二部分之上。

公开(公告)号：EP2901482A4

公开(公告)日：2016-05-11

申请号：EP13841180

申请日：2013-08-26

申请人： SILICON STORAGE TECH INC

发明人： SU CHIEN-SHENG ,  TADAYONI MANDANA ,  CHEN YUEH-HSIN

IPC分类号： H01L29/06 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66492 ,  H01L21/265 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/7833