公开(公告)号：EP3039712A4

公开(公告)日：2017-03-29

申请号：EP13892776

申请日：2013-08-30

Applicant: HEWLETT-PACKARD DEV COMPANY L P

Inventor： GE NING ,  CHIA LEONG YAP ,  LEE PIN CHIN ,  RANDO JOSE JEHROME

IPC: H01L21/336 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/66575 ,  H01L29/66659 ,  H05K2203/013

Abstract: A semiconductor device and method of forming the same is described. In an example, a polysilicon layer is deposited on a substrate having at least one polysilicon ring. The substrate is doped using the polysilicon layer as a mask to form doped regions in the substrate. A dielectric layer is deposited over the polysilicon layer and the substrate. The dielectric layer is etched to expose portions of the polysilicon layer. A metal layer is deposited on the dielectric layer. The metal layer, the dielectric layer, and the exposed portions of the polysilicon layer are etched such that at least a portion of each polysilicon ring is removed.

公开(公告)号：EP0928030B1

公开(公告)日：2009-02-11

申请号：EP97830744.5

申请日：1997-12-31

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico ,  Riva, Carlo

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L21/336 ,  H01L27/088

CPC classification number: H01L29/66575 ,  H01L21/823418 ,  H01L21/823443 ,  H01L27/088 ,  H01L27/105 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/7833

公开(公告)号：EP1649511A2

公开(公告)日：2006-04-26

申请号：EP04777187.8

申请日：2004-06-25

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： GHOZEIL, Adam, L. ,  STASIAK, James ,  PETERS, Kevin, F. ,  KAWAMOTO, Galen, H.

IPC: H01L21/8234 ,  H01L21/336 ,  H01L27/115 ,  H01L29/78

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L21/823437 ,  H01L29/1033 ,  H01L29/66575

Abstract: A nanoscopic transistor (20) is made by forming an oxide layer on a semiconductor substrate (S10, S20), applying resist (S30), patterning the resist using imprint lithography to form a pattern aligned along a first direction (S40), applying a first ion-masking material over the pattern (S50), selectively lifting it off to leave a first ion mask to form a gate (S60), forming doped regions by implanting a suitable dopant (S70), applying another layer of resist (S90) and patterning the second resist layer using imprint lithography to form a second pattern aligned along a second direction (S100), applying a second ion-masking material over the second pattern, selectively lifting it off to leave a second ion mask defined by the second pattern (S120), and forming second doped regions in the substrate by implanting a suitable second dopant selectively in accordance with the second ion mask (S130). The method may be used to make an array (10 or 15) of nanoscopic transistors (20).

公开(公告)号：EP0892424A3

公开(公告)日：2004-11-17

申请号：EP98304623.6

申请日：1998-06-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Clark, William F. ,  Ference, Thomas G. ,  Hook, Terence B. ,  Martin, Dale W.

IPC: H01L21/30

CPC classification number: H01L21/28211 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/28052 ,  H01L21/28176 ,  H01L21/28518 ,  H01L21/3003 ,  H01L21/31662 ,  H01L21/3185 ,  H01L21/324 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/665 ,  H01L29/66575

Abstract: Method of forming a film for a semiconductor device in which a source material comprising a deuterated species is provided during formation of the film.

公开(公告)号：EP1459366A2

公开(公告)日：2004-09-22

申请号：EP02781567.9

申请日：2002-11-20

Applicant: Koninklijke Philips Electronics N.V.

Inventor： STOLK, Peter, A.

IPC: H01L21/268 ,  H01L21/265 ,  H01L21/324 ,  H01L21/225 ,  H01L29/08 ,  H01L21/336

CPC classification number: H01L29/66575 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/268 ,  H01L21/324

Abstract: In the method of manufacturing a semiconductor device (1) with a semiconductor body (2), a doped zone (3) is formed in the semiconductor body (2). The semiconductor body (2) has a crystalline surface region (4), which crystalline surface region (4) is at least partly amorphized so as to form an amorphous surface layer (5). The amorphization is achieved by irradiating the surface (6) with a radiation pulse (7) which is absorbed by the crystalline surface region (4). The radiation pulse (7) has a wavelength which is chosen such that the radiation is absorbed by the crystalline surface region (4), and the energy flux of the radiation pulse (7) is chosen such that the crystalline surface layer (5) is melted. The method is useful for making ultra-shallow junctions.

公开(公告)号：EP1341233A2

公开(公告)日：2003-09-03

申请号：EP03003746.9

申请日：2003-02-19

Applicant: CANON KABUSHIKI KAISHA

Inventor： Kozuka, Hiraku ,  Iketa, Osamu ,  Shimotsusa, Mineo ,  Morii, Takashi

IPC: H01L27/092

CPC classification number: H01L29/7816 ,  H01L27/0922 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/66575 ,  H01L29/66681 ,  H01L29/7833

Abstract: A semiconductor device having a high source breakdown voltage and high performance and high reliability and a liquid jet apparatus are provided. In a semiconductor device having a switching element for flowing current through a load and a circuit for driving the switching element, respectively formed on the same substrate, the circuit has a source follower transistor for generating a drive voltage to be applied to a control electrode of the switching element, and the source region of the source follower transistor has a first doped region connected to the source electrode and a second doped region having an impurity concentration lower than that of the first doped region, the second doped region forming a pn junction with a semiconductor region forming a channel.

Abstract translation: 提供具有高源极击穿电压和高性能和高可靠性的半导体器件和液体喷射装置。 在具有用于流过负载的电流的开关元件和分别形成在同一衬底上的用于驱动开关元件的电路的半导体器件中，该电路具有源极跟随器晶体管，用于产生施加到控制电极的控制电极的驱动电压 源极跟随器晶体管的开关元件和源极区域具有连接到源电极的第一掺杂区域和具有低于第一掺杂区域的杂质浓度的第二掺杂区域，第二掺杂区域形成具有 形成通道的半导体区域。

公开(公告)号：EP1139409A3

公开(公告)日：2003-01-02

申请号：EP01301856.9

申请日：2001-02-28

Applicant: Agere Systems Guardian Corporation

Inventor： Kizilyalli, Isik C. ,  Radosevich, Joseph Rudolph ,  Roy, Pradip Kumar

IPC: H01L21/336 ,  H01L21/268 ,  H01L21/28 ,  H01L21/285

CPC classification number: H01L29/513 ,  H01L21/268 ,  H01L21/28176 ,  H01L21/76814 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/66659

Abstract: A method of manufacture for semiconductor electronic products and a circuit structure. A semiconductor material has a surface region and dopant is provided to a portion of the surface region. The portion of the surface region provided with the dopant is irradiated with sufficient energy to induce diffusion of the dopant from the portion of the surface region to another region of the semiconductor material. A method for manufacturing an electronic product with a semiconductor material having a surface and two spaced-apart regions along the surface for receiving dopant includes forming a field effect transistor gate structure is along the surface and over a third region of the surface between the two spaced-apart regions. Dopant is provided to the spaced-apart regions which are heated to a temperature at least 50 degrees C higher than the peak temperature which results in the third region when the spaced-apart regions are heated. A circuit comprises a semiconductor material having a surface region for formation of devices, a field effect transistor gate structure formed on the surface region, the gate structure including a conductive layer and an amorphous insulative layer having a dielectric constant greater than five relative to free space. The insulative layer is formed between the conductive layer and the surface region. A source region is formed along the surface region and a drain region is also formed along the surface region. The gate structure, source region and drain region are configured to form an operable field effect transistor.

公开(公告)号：EP1012879B1

公开(公告)日：2002-09-04

申请号：EP98909985.8

申请日：1998-01-29

Applicant: Ultratech Stepper Inc.

Inventor： TALWAR, Somit ,  KRAMER, Karl-Josef ,  VERMA, Guarav ,  WEINER, Kurt

IPC: H01L21/8238 ,  H01L21/225 ,  H01L21/265 ,  H01L21/336

CPC classification number: H01L29/66575 ,  H01L21/2254 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/0847 ,  Y10S148/061

Abstract: Pre-amorphization of a surface layer of crystalline silicon to an ultra-shallow (400) and (402) (e.g., less than 100 nm) depth provides a solution to fabrication problems including (a) high thermal conduction in crystalline silicon and (b) shadowing and diffraction-interference effects by an already fabricated gate of a field-effect transistor on incident laser radiation. Such problems, in the past, have prevented prior-art projection gas immersion laser doping from being effectively employed in the fabrication of integrated circuits comprising MOS field-effect transistors employing 100 nm and shallower junction technology.

公开(公告)号：EP1223610A1

公开(公告)日：2002-07-17

申请号：EP02368004.4

申请日：2002-01-15

Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, INC.

Inventor： Chan, Lap ,  Quek, Elgin ,  Sundaresan, Ravi ,  Pan, Yang ,  Lee, James Yong Meng ,  Leung, Ying Keung ,  Pradeep, Yelehanka Ramachandramurthy ,  Zheng, Jia Zhen

IPC: H01L21/336

CPC classification number: H01L29/66492 ,  H01L21/823814 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66575

Abstract: A method to form elevated source/drain (S/D) (62) over staircase shaped openings in insulating layers (28). A gate structure (14,16,18,24) is formed over a substrate (10). The gate structure is preferably comprised of a gate dielectric layer (14), gate electrode (16), first spacers (24), and a hard mask (18). A first insulating layer (28) is formed over the substrate and the gate structure. A resist layer (32) is formed having an opening over the gate structure and over a lateral area adjacent to the gate structure. The insulating layer is etched through the opening in the resist layer to form a source/drain (S/D) opening (40). The first spacers and hardmask are removed to form a source/drain (S/D) contact opening (50). Ions are implanted to form lightly doped drain regions. Second spacers are formed on the sidewalls of the gate electrode and the gate dielectric and on the sidewalls of the insulating layer in the source/drain (S/D) contact opening and the source/drain (S/D) opening. A conductive layer is deposited and planarized to form elevated source/drain (S/D) blocks (62) on a staircase shape insulating layer (28).

Abstract translation: 的方法，在上绝缘层（28）的楼梯形开口形成升高的源极/漏极（S / D）（62）。 的栅极结构（14,16,18,24）形成在基板（10）。 栅极结构最好包括一栅极介电层（14），栅电极（16），第一间隔物（24），以及硬掩模（18）的。 第一绝缘层（28）形成在所述衬底和所述栅极结构。 的抗蚀剂层（32）被形成为具有开口，以在所述栅极结构和在横向区域毗邻栅极结构。 该绝缘层是通过在抗蚀剂层中的开口蚀刻以形成源极/漏极（S / D）开口（40）。 所述第一间隔物和硬掩模被除去，以形成源极/漏极（S / D）接触开口（50）。 离子注入，以形成轻度掺杂的漏区。 第二间隔物形成于栅电极和所述栅极电介质的侧壁和在所述源极/漏极（S / D）接触开口和所述源极/漏极（S / D）开口的绝缘层的侧壁上。 导电层被沉积和平坦化，以形成阶梯形绝缘层（28）上提升的源极/漏极（S / D）的块（62）。

公开(公告)号：EP0715769B1

公开(公告)日：2002-03-06

申请号：EP94923248.2

申请日：1994-06-24

Applicant: NATIONAL SEMICONDUCTOR CORPORATION

Inventor： DEMIRLIOGLU, Esin, Kutlu ,  ARONOWITZ, Sheldon

IPC: H01L21/225 ,  H01L21/82 ,  H01L21/336

CPC classification number: H01L29/66575 ,  H01L21/2254 ,  H01L21/823835 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/665 ,  H01L29/66545

Abstract: A method for manufacturing CMOS semiconductor devices wherein damage to the active regions of the devices due to the direct implantation of impurities is suppressed. A material is selectively deposited on a semiconductor substrate, the material having a characteristic such that formation of the material occurs on some substances such as silicon and polysilicon, and formation of the material is suppressed on other substances such as silicon dioxide and silicon nitride. Impurities are introduced into the material rather than into the substrate. The impurities are then diffused into the active regions by standard processes such as rapid thermal anneal (RTA) or furnace anneal. The material generally contains germanium, and usually is a polycrystalline silicon-germanium alloy. The diffusion depth of the impurities may be controlled with great precision by manipulating several parameters. The parameters include the thickness of the material, the energy of the impurity implants, the density of the impurity implants, and the concentration of germanium in the material.