-
1.
公开(公告)号:EP4150621A1
公开(公告)日:2023-03-22
申请号:EP20824005.1
申请日:2020-11-16
发明人: TRAN, Hieu Van , VU, Thuan , HONG, Stanley , TRINH, Stephen , TRAN, Han , TIWARI, Vipin , PHAM, Hien
-
公开(公告)号:EP4407874A2
公开(公告)日:2024-07-31
申请号:EP24181465.6
申请日:2020-09-03
发明人: TRAN, Hieu Van , VU, Thuan , TRINH, Stephen , HONG, Stanley , LY, Anh , TIWARI, Vipin
IPC分类号: H03M1/56
CPC分类号: G11C7/12 , G11C7/14 , G11C11/54 , G11C16/0425 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3427 , H03F3/45475 , H03F2203/4552620130101 , H03F2203/4553620130101 , H03M1/468 , H03M1/164 , H03M1/145 , G06N3/063 , H03M1/56 , G06N3/065 , G06N3/048 , G06N3/045
摘要: Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.
-
3.
公开(公告)号:EP4162491A1
公开(公告)日:2023-04-12
申请号:EP20828619.5
申请日:2020-11-27
发明人: TRAN, Hieu Van , VU, Thuan , TRINH, Stephen , HONG, Stanley , LY, Anh
-
公开(公告)号:EP4128239A1
公开(公告)日:2023-02-08
申请号:EP20786400.0
申请日:2020-09-22
发明人: TRAN, Hieu Van , VU, Thuan , TRINH, Stephen , HONG, Stanley , LY, Anh , LEMKE, Steven , TIWARI, Vipin , DO, Nhan
-
公开(公告)号:EP4115423A1
公开(公告)日:2023-01-11
申请号:EP20781134.0
申请日:2020-09-03
发明人: TRAN, Hieu Van , VU, Thuan , TRINH, Stephen , HONG, Stanley , LY, Anh , TIWARI, Vipin
-
公开(公告)号:EP3963513A1
公开(公告)日:2022-03-09
申请号:EP19817533.3
申请日:2019-11-18
发明人: TRAN, Hieu Van , TRINH, Stephen , VU, Thuan , HONG, Stanley , TIWARI, Vipin , REITEN, Mark , DO, Nhan
IPC分类号: G06N3/063
-
7.
公开(公告)号:EP4401080A3
公开(公告)日:2024-10-02
申请号:EP24177589.9
申请日:2019-09-05
发明人: TRAN, Hieu Van , VU, Thuan , TRINH, Stephen , LY, Anh , HONG, CA Stanley
IPC分类号: G11C11/54 , G11C16/12 , G11C16/14 , G11C16/16 , G11C16/24 , G11C16/30 , G06N3/04 , G06N3/063 , G11C16/34 , G11C27/00 , G11C7/12 , G11C8/08 , G06N3/048 , G06N3/065 , G06F12/02 , G06N3/044 , G06N3/045 , G06N3/08 , G11C7/10 , G11C16/04 , G11C16/10
CPC分类号: G11C11/54 , G11C16/3459 , G11C27/005 , G06N3/08 , G11C16/24 , G11C7/1006 , G11C16/10 , G11C16/0425 , G11C16/0433 , G06F12/0246 , G06F2212/720120130101 , G06F2212/720220130101 , G06N3/065 , G06N3/048 , G06N3/044 , G06N3/045 , G11C7/12 , G11C8/08
摘要: Various embodiments of high voltage generation circuits, high voltage operational amplifiers, adaptive high voltage supplies, adjustable high voltage incrementor, adjustable reference supplies, and reference circuits are disclosed. These circuits optionally can be used for programming a non-volatile memory cell in an analog neural memory to store one of many possible values.
-
公开(公告)号:EP4280113A3
公开(公告)日:2024-05-08
申请号:EP23201693.1
申请日:2019-09-07
发明人: TRAN, Hieu Van , VU, Thuan , TRINH, Stephen , HONG, Stanley , LY, Anh
IPC分类号: G11C11/54 , G11C16/12 , G11C16/14 , G06F12/02 , G11C16/16 , G11C16/24 , G11C16/30 , G06N3/04 , G06N3/063 , G11C16/34 , G11C27/00 , G06N3/048 , G06N3/045 , G06N3/044 , G06N3/08 , G06N3/065 , G11C16/10 , G11C16/04 , G11C7/10
CPC分类号: G11C11/54 , G11C16/3459 , G11C27/005 , G06N3/08 , G11C16/24 , G11C7/1006 , G11C16/10 , G11C16/0425 , G11C16/0433 , G06F12/0246 , G06F2212/720120130101 , G06F2212/720220130101 , G06N3/065 , G06N3/048 , G06N3/044 , G06N3/045
摘要: Various algorithms are disclosed for verifying the stored weight in a non-volatile memory cell in a neural network following a multilevel programming operation of the non-volatile memory cell by converting the stored weight into a plurality of digital output bits. Circuity, such as an adjustable reference current source, for implementing the algorithms are disclosed.
-
公开(公告)号:EP4280113A2
公开(公告)日:2023-11-22
申请号:EP23201693.1
申请日:2019-09-07
发明人: TRAN, Hieu Van , VU, Thuan , TRINH, Stephen , HONG, Stanley , LY, Anh
IPC分类号: G06N3/065
摘要: Various algorithms are disclosed for verifying the stored weight in a non-volatile memory cell in a neural network following a multilevel programming operation of the non-volatile memory cell by converting the stored weight into a plurality of digital output bits. Circuity, such as an adjustable reference current source, for implementing the algorithms are disclosed.
-
10.
公开(公告)号:EP4150620A1
公开(公告)日:2023-03-22
申请号:EP20811911.5
申请日:2020-10-30
发明人: TRAN, Hieu Van , TRINH, Stephen , VU, Thuan , LEMKE, Steven , TIWARI, Vipin , DO, Nhan , HONG, Stanley
-
-
-
-
-
-
-
-
-