公开(公告)号：EP0865154B1

公开(公告)日：2004-02-11

申请号：EP98301616.3

申请日：1998-03-04

申请人： STMicroelectronics, Inc.

发明人： Brady, James

IPC分类号： H03B1/04 ,  H03B5/32 ,  G06F1/18

CPC分类号： H03B5/32 ,  G06F1/182 ,  H03B1/04

公开(公告)号：EP0982735A2

公开(公告)日：2000-03-01

申请号：EP99306570.5

申请日：1999-08-19

申请人： STMicroelectronics, Inc.

发明人： Brady, James ,  Worley, James L.

IPC分类号： G11C7/00 ,  G11C11/409

CPC分类号： G11C7/12

摘要： A bit line recovery circuit for random access memory. The circuit includes a pair of pull-up devices, each of which is connected to a bit line of a bit line pair. Pass gates are disposed between a sense amplifier and the bit lines. The pull-up devices are cross-coupled such that the gate node of the pull-up devices are connected to the sense amplifier on the opposed side of the pass gates in order to rapidly turn on the appropriate pull-up device following a memory cell read operation.

公开(公告)号：EP0590982B1

公开(公告)日：1999-03-03

申请号：EP93307776.0

申请日：1993-09-30

申请人： STMicroelectronics, Inc.

发明人： McClure, David Charles ,  Brady, James

IPC分类号： G11C29/00

CPC分类号： G11C29/34 ,  G11C11/41 ,  G11C29/50

公开(公告)号：EP0982735A3

公开(公告)日：2001-01-17

申请号：EP99306570.5

申请日：1999-08-19

申请人： STMicroelectronics, Inc.

发明人： Brady, James ,  Worley, James L.

IPC分类号： G11C7/00 ,  G11C11/409

CPC分类号： G11C7/12

摘要： A bit line recovery circuit for random access memory. The circuit includes a pair of pull-up devices, each of which is connected to a bit line of a bit line pair. Pass gates are disposed between a sense amplifier and the bit lines. The pull-up devices are cross-coupled such that the gate node of the pull-up devices are connected to the sense amplifier on the opposed side of the pass gates in order to rapidly turn on the appropriate pull-up device following a memory cell read operation.

公开(公告)号：EP0997911A1

公开(公告)日：2000-05-03

申请号：EP99308491.2

申请日：1999-10-27

申请人： STMicroelectronics, Inc.

发明人： Brady, James

IPC分类号： G11C11/409 ,  G11C7/12

CPC分类号： G11C11/4094 ,  G11C7/12

摘要： A circuit for clamping the voltage appearing on the bit lines of a dynamic random access memory (DRAM) device so that the voltage thereon is maintained above the low reference voltage source. The circuit includes pull-up devices connected to the bit lines of the DRAM device. The pull-up devices are active only when pull-down devices connected to the bit lines pull some of the bit lines towards the low reference voltage level.

摘要翻译： 用于钳位出现在动态随机存取存储器（DRAM）器件的位线上的电压使得其上的电压保持在低参考电压源之上的电路。 电路包括连接到DRAM器件的位线的上拉器件。 只有当连接到位线的下拉器件将某些位线拉向低参考电压电平时，上拉器件才有效。

公开(公告)号：EP1006444A3

公开(公告)日：2005-08-03

申请号：EP99308492.0

申请日：1999-10-27

申请人： STMicroelectronics, Inc.

发明人： Brady, James

IPC分类号： G06F11/00 ,  G11C29/00

CPC分类号： G11C29/34

摘要： A method and apparatus for testing a random access memory device, such as a dynamic random access memory device embedded within an integrated circuit chip. The apparatus includes one or more rows of transistors, each of which is connected to a bit line pair of the memory device and to a data line. Data is placed onto the bit lines by driving the data line to a predetermined voltage level and turning on the transistors in the transistor row. Data placed on the bit lines forms a test pattern that may be subsequently written into any row of memory cells. By directly controlling the bit lines of the memory device in this way, test patterns may be quickly and easily stored in the memory device for functional verification thereof.

公开(公告)号：EP0929050A3

公开(公告)日：2001-01-10

申请号：EP99300181.7

申请日：1999-01-12

申请人： STMicroelectronics, Inc.

发明人： Kramer, Alan ,  Brady, James

IPC分类号： G06K9/00

CPC分类号： G06K9/0002

摘要： A scanning fingerprint detection system that includes an array of capacitive sensing elements. The array has a first dimension greater than the width of a fingerprint and a second dimension less than the length of a fingerprint. Each of the capacitive sensing elements has a size less than the width of a fingerprint ridge. Circuitry is provided for scanning the array to capture an image of a portion of fingerprint and for assembling the captured images into a fingerprint image as a fingerprint is moved over the array.

公开(公告)号：EP1049104A1

公开(公告)日：2000-11-02

申请号：EP00303623.3

申请日：2000-04-28

申请人： STMicroelectronics, Inc.

发明人： Brady, James

IPC分类号： G11C29/00

CPC分类号： G11C29/02 ,  G11C29/52

摘要： For testing memory circuitry a first address signal is applied to a row decode circuit to activate a wordline, and a second address signal is applied to a column decode circuit to access a bitline. A write data signal is stored in a first storage circuit and written to a particular memory cell that is connected to both the activated wordline and the accessed bitline. A read data signal is read from the particular cell and then stored in a second storage circuit. The stored write and read data signals are then compared to test for proper circuit operation.

摘要翻译： 为了测试存储器电路，第一地址信号被施加到行解码电路以激活字线，并且第二地址信号被施加到列解码电路以访问位线。 写数据信号存储在第一存储电路中，并写入连接到激活的字线和被访问位线的特定存储单元。 从特定单元读取读取数据信号，然后存储在第二存储电路中。 然后将存储的写入和读取数据信号进行比较，以测试正确的电路操作。

公开(公告)号：EP1049017A1

公开(公告)日：2000-11-02

申请号：EP00303618.3

申请日：2000-04-28

申请人： STMicroelectronics, Inc.

发明人： Brady, James

IPC分类号： G06F11/20

CPC分类号： G11C29/78

摘要： A redundant circuit for a semiconductor memory device includes a programmable circuit for selectively generating at least one first address corresponding to a defective memory row or column line, and shifter circuitry for remapping second addresses which are greater than the first address to row/column lines. For each second address which is greater than the first address, the shifter circuitry remaps the second address to a row/column line which was initially mapped to an immediately higher address relative to the second address.

摘要翻译： 用于半导体存储器件的冗余电路包括用于选择性地产生对应于有缺陷的存储器行或列线的至少一个第一地址的可编程电路和用于将大于第一地址的第二地址重新映射到行/列线的移位器电路。 对于大于第一地址的每个第二地址，移位器电路将第二地址重新映射到最初映射到相对于第二地址的立即更高地址的行/列线。

公开(公告)号：EP0987717A1

公开(公告)日：2000-03-22

申请号：EP99306571.3

申请日：1999-08-19

申请人： STMicroelectronics, Inc.

发明人： Brady, James

IPC分类号： G11C29/00

CPC分类号： G11C29/50012 ,  G11C11/401 ,  G11C29/50

摘要： Reduction of time for determining a memory refresh frequency for a dynamic random access memory includes disabling the bootstrap circuitry associated with a word line when writing data into a memory cell during a test operation. When data representing a high logic level is written into the memory cell, the resulting charge that is stored is less than the stored charge under normal operation of the dynamic memory. Consequently, the decay time for the stored charge is shortened, thereby shortening the time for testing the refresh frequency of the memory cell.

摘要翻译： 用于确定用于动态随机存取存储器的存储器刷新频率的时间的减少包括在测试操作期间将数据写入存储器单元时禁用与字线相关联的引导电路。 当表示高逻辑电平的数据被写入存储单元时，存储的结果电荷小于动态存储器的正常操作下存储的电荷。 因此，存储电荷的衰减时间缩短，从而缩短了测试存储单元刷新频率的时间。