公开(公告)号：EP4187415A1

公开(公告)日：2023-05-31

申请号：EP22205161.7

申请日：2022-11-02

申请人： STMicroelectronics Application GmbH ,  STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

发明人： ZARGAR, Asif Rashid ,  GROSSIER, Nicolas Bernard ,  JAIN, Charul ,  COLOMBO, Roberto

IPC分类号： G06F21/44 ,  G06F21/55 ,  G06F21/76 ,  G06F21/79 ,  G06F21/85

摘要： A processing system (10a) is described. The processing system (10a) comprises a plurality of storage elements (113), wherein each storage element (113) is configured to receive a write request comprising a data bit (DATA) and store the received data bit (DATA) to a latch or flip-flop (1122). A hardware circuit (110, 150, 152, 1130, 1502) is configured to change operation as a function of the logic level stored to the latch or flip-flop (1122) of a first storage element (113) of the plurality of storage elements (113). A non-volatile memory (104; 126) is configured to store data bits (CD, LCD) for the plurality of storage elements (113) and a hardware configuration circuit (108) is configured to read the data bits from the non-volatile memory (104; 126) and generate write requests in order to store the data bits to the storage elements (113).
Specifically, the hardware circuit (110, 150, 152, 1130, 1502) is configured to change operation also as a function of the first tamper signal (TAMP). For this purpose, the first storage element (113) comprises a further latch or flip-flop (1124) and is configured to store, in response to the write request, the inverted version (1126) of the received data bit to the further latch or flip-flop (1124). The first storage element (113) comprises also a combinational logic circuit (1128) configured to compare the logic level stored to the latch or flip-flop (1122) of the first storage element (113) with the logic level stored to the further latch or flip-flop (1122) of the first storage element (113). The combinational logic circuit (1128) is configured to de-assert a first tamper signal (TAMP) associated with the first storage element (113) when the logic levels are different, and assert the first tamper signal (TAMP) when the logic levels are the same.

公开(公告)号：EP3929783A1

公开(公告)日：2021-12-29

申请号：EP21177854.3

申请日：2021-06-04

申请人： STMicroelectronics (ALPS) SAS ,  STMicroelectronics International N.V.

发明人： ZARGAR, Asif Rashid ,  EYZAT, Gilles ,  JAIN, Charul

IPC分类号： G06F21/55 ,  G06F11/30 ,  G06F11/22 ,  G06F21/76

摘要： A system on a chip comprising a set of one-time programmable memory elements that comprises a first valid configuration; a second valid configuration; and a plurality of invalid configurations. The system on a chip also comprises a programming indicator initially comprising a first value and configured to be permanently set to a second value. The system on a chip further comprises a decoder circuit in communication with the set of one-time programmable memory elements to determine whether the set of one-time programmable memory elements is in the first valid configuration, the second valid configuration, or any one of the plurality of invalid configurations. The decoder circuit generates a threat-detection signal when the set of one-time programmable memory elements is in any of the plurality of invalid configurations when the programming indicator is permanently set to the second value.

公开(公告)号：EP4036734A1

公开(公告)日：2022-08-03

申请号：EP22151175.1

申请日：2022-01-12

申请人： STMicroelectronics International N.V.

发明人： JAIN, Charul ,  ZARGAR, Asif Rashid

IPC分类号： G06F11/16 ,  G06F11/00 ,  H03K19/003

摘要： An apparatus includes a primary processor (102) and a secondary processor (104) configured to receive a first signal, a second signal and a plurality of input signals, and perform same operations as each other based on the first signal, the second signal and the plurality of input signals, a comparison circuit (112) configured to receive output signals of the primary processor (102) and the secondary processor (104), and detect a lockstep mismatch between the primary processor and the secondary processor based on the output signals, a fault capturing circuit (114) configured to receive the first signal and the second signal, and capture a fault signal generated by the comparison circuit (112), and a first glitch absorption device (116) configured to receive the first signal and the second signal, and absorb glitches fed into the first glitch absorption device (116).