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公开(公告)号：EP4212983A1
公开(公告)日：2023-07-19
申请号：EP23160273.1
申请日：2015-12-29
摘要： A circuit arrangement for the generation of a bandgap voltage reference in CMOS technology, of the type that includes a circuit module (101; 101') for generation of a base-emitter voltage difference comprising at least one pair of PNP bipolar substrate transistors, which comprises a first bipolar substrate transistor (Q1) inserted in a first circuit branch (B1) that identifies a first current path (11) from the supply voltage (Vdd) to ground (GND), and a second bipolar substrate transistor (Q2) inserted in a second circuit branch (B2) that identifies a second current path (12) from the supply voltage (Vdd) to ground (GND), said first bipolar substrate transistor (Q1) and second bipolar substrate transistor (Q2) being connected together via their base electrode, and the second transistor (Q2) having an aspect ratio (N) higher than that of the first transistor (Q), said circuit arrangement (100; 200; 200'; 200"; 300; 300'; 300"; 400; 400'; 400") comprising a first CMOS current mirror (102; 402; 402') of an n type, connected between said first branch (B1) and said second branch (B2) and connected via a resistance (R1) for adjustment of the bandgap reference voltage to the second bipolar transistor (Q1), a second CMOS current mirror (103; 103'; 403, 403") of a p type, connected between said first branch (B1) and said second branch (B2), said first current mirror (102; 402; 402') and second current mirror (103; 103'; 403, 403") being connected so that each current mirror repeats the current of the other. Said circuit module (101) for generation of a base-emitter voltage difference comprises just said first bipolar substrate transistor (Q1) inserted in the first circuit branch (B1) and said second bipolar substrate transistor (Q2) inserted in the second circuit branch (B2), the current that flows in said circuit arrangement (100; 200; 200'; 200"; 300; 300'; 300"; 400; 400'; 400") from the supply voltage (Vdd) to ground (GND) flowing only through said first bipolar substrate transistor (Q1) and said second bipolar substrate transistor (Q2).
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公开(公告)号：EP3352355A1
公开(公告)日：2018-07-25
申请号：EP17190831.2
申请日：2017-09-13
摘要： A charge pump circuit comprises:
- a charge pump (CP) with an input voltage (V R ) and an output voltage (V CP ) which is a multiple N of the input voltage (V R ), the charge pump (CP) having a clock input (CLK),
- an input stage (10) with a reference terminal for receiving a reference voltage (V REF ) and an output terminal coupled to the charge pump (CP) for applying the input voltage (V R ) to the charge pump (CP), and
- at least one output capacitance (C OUT ) coupled (14, 16) to the charge pump (CP) and chargeable to an output voltage (V OUT ) of the circuit.
The circuit comprises:
- a feedback network (14, 16) comprising a first feedback loop (14) for feeding back the output voltage (V CP ) of the charge pump (CP) towards the input of the input stage (10) and a second feedback loop (16a, 16b, 16c) for maintaining a fixed offset between the output voltage (V CP ) of the charge pump (CP) and the output voltage (V OUT ) of the circuit, and/or
- the output capacitance (C OUT ) being divided between two output capacitors (α.C OUT ; (1-α).C OUT ) with a switch (S1) set between the two capacitors and driven by a driver unit (20) coupled to the clock input (CLK) of the charge pump (CP), with the switch (S1) which is opened at switching edges of the clock signal (CLK) at the clock input (CLK) of the charge pump (CP).-
公开(公告)号：EP3352355B1
公开(公告)日：2020-03-11
申请号：EP17190831.2
申请日：2017-09-13
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公开(公告)号：EP3098195A1
公开(公告)日：2016-11-30
申请号：EP15200289.5
申请日：2015-12-15
发明人： BRUNO, Giuseppe , CONTI, Sebastiano , CHIRICOSTA, Mario , VAIANA, Michele , IPPOLITO, Calogero Marco , MAIORE, Mario , CASELLA, Daniele
CPC分类号： B81B7/007 , B81B7/02 , B81B2201/0264 , B81B2201/0292 , B81B2207/094 , G01L19/0092 , G01N27/223 , H01L23/3121 , H01L2224/32145 , H01L2224/48091 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00014
摘要： A packaged sensor assembly includes: a packaging structure (2), having at least one opening (18); a humidity sensor (5) and a pressure sensor (10), which are housed inside the packaging structure (2) and communicate fluidically with the outside through the opening (18), and a control circuit (7), operatively coupled to the humidity sensor (5) and to the pressure sensor (10);
wherein the humidity sensor (5) and the control circuit (7) are integrated in a first chip (3), and the pressure sensor (10) is integrated in a second chip (8) distinct from the first chip (3) and bonded to the first chip (3).摘要翻译： 包装传感器组件包括：具有至少一个开口（18）的包装结构（2）; 湿度传感器（5）和压力传感器（10），其容纳在所述包装结构（2）内并通过所述开口（18）与所述外部流体连通;以及控制电路（7），其可操作地耦合到所述湿度 传感器（5）和压力传感器（10）; 其中所述湿度传感器（5）和所述控制电路（7）集成在第一芯片（3）中，并且所述压力传感器（10）集成在与所述第一芯片（3）不同的第二芯片（8）中并且 到第一芯片（3）。
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5.发明公开CIRCUIT ARRANGEMENT FOR THE GENERATION OF A BANDGAP REFERENCE VOLTAGE 审中-公开SCH UN OR UNG UNG DS DS DS DS DS DS DS DS DS DS DS DS
公开(公告)号：EP3091418A1
公开(公告)日：2016-11-09
申请号：EP15202867.6
申请日：2015-12-29
IPC分类号： G05F3/30
摘要： A circuit arrangement for the generation of a bandgap voltage reference in CMOS technology, of the type that includes a circuit module (101; 101') for generation of a base-emitter voltage difference comprising at least one pair of PNP bipolar substrate transistors, which comprises a first bipolar substrate transistor (Q1) inserted in a first circuit branch (B1) that identifies a first current path (I1) from the supply voltage (Vdd) to ground (GND), and a second bipolar substrate transistor (Q2) inserted in a second circuit branch (B2) that identifies a second current path (12) from the supply voltage (Vdd) to ground (GND), said first bipolar substrate transistor (Q1) and second bipolar substrate transistor (Q2) being connected together via their base electrode, and the second transistor (Q2) having an aspect ratio (N) higher than that of the first transistor (Q), said circuit arrangement (100; 200; 200'; 200"; 300; 300'; 300"; 400; 400'; 400") comprising a first CMOS current mirror (102; 402; 402') of an n type, connected between said first branch (B1) and said second branch (B2) and connected via a resistance (R1) for adjustment of the bandgap reference voltage to the second bipolar transistor (Q1), a second CMOS current mirror (103; 103'; 403, 403") of a p type, connected between said first branch (B1) and said second branch (B2), said first current mirror (102; 402; 402') and second current mirror (103; 103'; 403, 403") being connected so that each current mirror repeats the current of the other. Said circuit module (101) for generation of a base-emitter voltage difference comprises just said first bipolar substrate transistor (Q1) inserted in the first circuit branch (B1) and said second bipolar substrate transistor (Q2) inserted in the second circuit branch (B2), the current that flows in said circuit arrangement (100; 200; 200'; 200"; 300; 300'; 300"; 400; 400'; 400") from the supply voltage (Vdd) to ground (GND) flowing only through said first bipolar substrate transistor (Q1) and said second bipolar substrate transistor (Q2).
摘要翻译： 一种用于在CMOS技术中产生带隙电压参考的电路装置，其类型包括用于产生包含至少一对PNP双极衬底晶体管的基极 - 发射极电压差的电路模块（101; 101'），其中 包括插入在从电源电压（Vdd）到地（GND）识别第一电流路径（I1）的第一电路分支（B1）中的第一双极衬底晶体管（Q1）和插入的第二双极衬底晶体管 在从电源电压（Vdd）到地（GND）识别第二电流路径（12）的第二电路支路（B2）中，所述第一双极晶体管（Q1）和第二双极晶体管（Q2）经由 所述电路装置（100; 200; 200'; 200“; 300; 300”; 300“; 300”; 300“; 300”; 300“; 300” ; 400; 400'; 400“），包括第一CMOS电流镜（10 2; 402; 402），连接在所述第一分支（B1）和所述第二分支（B2）之间并通过用于调整带隙参考电压的电阻（R1）连接到第二双极晶体管（Q1），第二CMOS 连接在所述第一分支（B1）和所述第二分支（B2）之间的所述第一电流镜（102; 402; 402'）和所述第二电流镜（103; 103; 103'; 403,403“）连接，使得每个电流镜重复另一个的电流。 用于产生基极 - 发射极电压差的所述电路模块（101）仅包括插入在第一电路支路（B1）中的所述第一双极衬底晶体管（Q1）和插入第二电路支路（B1）中的所述第二双极衬底晶体管 B2），从电源电压（Vdd）到地（GND）的所述电路布置（100; 200; 200'; 200“; 300; 300”; 300“; 400; 400”; 400“ 仅流过所述第一双极衬底晶体管（Q1）和所述第二双极衬底晶体管（Q2）。
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