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1.发明公开Device for converting a differential signal to a single signal 有权一种用于差分输入信号转换成Eintaktausgangssignal
公开(公告)号：EP1376861A3
公开(公告)日：2004-05-19
申请号：EP03076840.2
申请日：2003-06-13
IPC分类号： H03F3/45
CPC分类号： H03F3/45085 , H03F3/45089 , H03F2203/45296 , H03F2203/45392 , H03F2203/45394 , H03F2203/45702
摘要： A device for converting a differential signal (Vin1, Vin2) to a single signal (Vout) is described. The device comprises at least one pair of transistors (Q1, Q2) having equal transconductance gain (gm) and which are arranged according a differential stage configuration. The transistors (Q1, Q2) have the differential signal (Vin1, Vin2) in input at the drivable terminals, have first non drivable terminals coupled respectively to first terminals of a first (R1) and a second (Rout) passive elements having second terminals connected with a first supply voltage (VDD), second non drivable terminals coupled to a second supply voltage (VEE) lower than the first supply voltage (VDD). The first terminal of the second passive element (Rout) is the output terminal (OUT) of the device. The last comprises a further transistor (Q3) having a first non drivable terminal connected with the output terminal (OUT) of the device, a second non drivable terminal coupled with said second supply voltage (VEE) and the drivable terminal connected with the first terminal of the first passive element (R1). The further transistor (Q3) has such a transconductance gain (gm3) that the product of said transconductance gain (gm3) by said first passive element (R1) is unitary.
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2.发明公开
公开(公告)号：EP1061428A1
公开(公告)日：2000-12-20
申请号：EP99830374.7
申请日：1999-06-16
IPC分类号： G05F1/575
CPC分类号： G05F1/575
摘要： The invention relates to a low-drop type of voltage regulator (1) formed with BiCMOS/CMOS technology and being of the type which comprises: an input terminal (IN), receiving a stable voltage reference (Vrif) and being connected to one input (-) of an operational amplifier (2) through a switch controlled by a power-on enable signal (CE); a supply voltage reference (Vpos) powering the operational amplifier (2); an output transistor (M1) connected to an output (U) of the amplifier (2) to generate a regulated voltage value (Vreg) to be fed back to the amplifier (2) input; a second transistor (M2) connected in series between the output transistor (M1) and the supply voltage reference (Vpos). The regulator of this invention comprises a control circuit portion (7) connected between the control terminal of the second transistor (M2) and the supply voltage reference (Vpos) to prevent the breakdown of the output transistor (M1) from occurring.
摘要翻译： 本发明涉及一种用BiCMOS / CMOS技术形成的低压型电压调节器（1），其特征在于包括：输入端（IN），接收稳定的电压基准（Vrif）并连接到一个输入端 （ - ）通过由上电使能信号（CE）控制的开关; 为运算放大器（2）供电的电源电压参考（Vpos）; 连接到放大器（2）的输出（U）的输出晶体管（M1），以产生要反馈到放大器（2）输入端的调节电压值（Vreg）; 串联连接在输出晶体管（M1）和电源电压基准（Vpos）之间的第二晶体管（M2）。 本发明的调节器包括连接在第二晶体管（M2）的控制端和电源电压基准（Vpos）之间的控制电路部分（7），以防止输出晶体管（M1）的击穿。
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3.发明公开Device for converting a differential signal to a single signal 有权Vorrichtung zur Umwandlung eines在Ein Eintaktausgangssignal的Differentialzeingangsignals
公开(公告)号：EP1376861A2
公开(公告)日：2004-01-02
申请号：EP03076840.2
申请日：2003-06-13
IPC分类号： H03F3/45
CPC分类号： H03F3/45085 , H03F3/45089 , H03F2203/45296 , H03F2203/45392 , H03F2203/45394 , H03F2203/45702
摘要： A device for converting a differential signal (Vin1, Vin2) to a single signal (Vout) is described. The device comprises at least one pair of transistors (Q1, Q2) having equal transconductance gain (gm) and which are arranged according a differential stage configuration. The transistors (Q1, Q2) have the differential signal (Vin1, Vin2) in input at the drivable terminals, have first non drivable terminals coupled respectively to first terminals of a first (R1) and a second (Rout) passive elements having second terminals connected with a first supply voltage (VDD), second non drivable terminals coupled to a second supply voltage (VEE) lower than the first supply voltage (VDD). The first terminal of the second passive element (Rout) is the output terminal (OUT) of the device. The last comprises a further transistor (Q3) having a first non drivable terminal connected with the output terminal (OUT) of the device, a second non drivable terminal coupled with said second supply voltage (VEE) and the drivable terminal connected with the first terminal of the first passive element (R1). The further transistor (Q3) has such a transconductance gain (gm3) that the product of said transconductance gain (gm3) by said first passive element (R1) is unitary.
摘要翻译： 描述用于将差分信号（Vin1，Vin2）转换为单个信号（Vout）的装置。 该器件包括具有相等跨导增益（gm）的至少一对晶体管（Q1，Q2），并且根据差分级配置布置。 晶体管（Q1，Q2）在可驱动端子处输入的差分信号（Vin1，Vin2）具有分别耦合到具有第二端子（R1）的第一端（R1）和第二（Rout）无源元件的第一不可驱动端子 与第一电源电压（VDD）连接，第二不可驱动端子耦合到低于第一电源电压（VDD）的第二电源电压（VEE）。 第二无源元件（Rout）的第一个端子是器件的输出端子（OUT）。 最后一个包括具有与该装置的输出端（OUT）连接的第一不可驱动端子的另一个晶体管（Q3），与所述第二电源电压（VEE）耦合的第二不可驱动端子和与第一端子 的第一无源元件（R1）。 另外的晶体管（Q3）具有这样的跨导增益（gm3），所述第一无源元件（R1）的所述跨导增益（gm3）的乘积是一体的。
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公开(公告)号：EP1047194A1
公开(公告)日：2000-10-25
申请号：EP99830239.2
申请日：1999-04-23
IPC分类号： H03K19/013 , H03K5/24 , H03F3/30
CPC分类号： H03F3/3071 , H03K5/2418 , H03K19/0136
摘要： A clipping stage, particularly for high frequencies, which comprises:
a first power supply line (V CC ) and a second power supply line (V EE );
a differential input stage which is constituted by a first transistor (Q1) and a second transistor (Q2), is supplied by a first current source (Q4, R4) and is interposed between said first power supply line and said second power supply line;
a third transistor (Q3) which is connected between said first power supply line and said second power supply line and to said input stage and is supplied with power by a second current source (Q5, R5);
an output stage which is connected to said input stage and to an output load (R L , C L );
the particularity of which consists of the fact that the stage further comprises an active load (Q8) which is arranged in parallel to said output load (R L , C L ) and means (C) for driving said active load (Q8) which are suitable to drive the starting of a current pulse from said third transistor (Q3) to said active load (Q8), in order to provide a faster falling front of the output signal of said output stage.摘要翻译： 包括由电流源（Q4，R4）提供的两个晶体管（Q1，Q2）的差分输入级连接在两条电源线之间。 连接在线路和输入级之间的第三晶体管（Q3）由第二电流源（Q5，R5）提供。 输出级连接到与驱动（C）的有源负载（Q8）并联的输出负载，以便从第三晶体管启动电流脉冲，从而提供输出信号的更快的下降沿。
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公开(公告)号：EP1630951B1
公开(公告)日：2008-03-05
申请号：EP04425635.2
申请日：2004-08-26
发明人： Pelleriti, Roberto
IPC分类号： H03F1/56
CPC分类号： H03F1/56 , H03F1/26 , H03F3/183 , H03F3/45103 , H03F2200/372 , H03F2203/45492 , H03F2203/45722
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7.发明授权Device for converting a differential signal to a single signal 有权一种用于差分输入信号转换成Eintaktausgangssignal
公开(公告)号：EP1376861B1
公开(公告)日：2009-03-25
申请号：EP03076840.2
申请日：2003-06-13
IPC分类号： H03F3/45
CPC分类号： H03F3/45085 , H03F3/45089 , H03F2203/45296 , H03F2203/45392 , H03F2203/45394 , H03F2203/45702
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公开(公告)号：EP1630951A1
公开(公告)日：2006-03-01
申请号：EP04425635.2
申请日：2004-08-26
发明人： Pelleriti, Roberto
IPC分类号： H03F1/56
CPC分类号： H03F1/56 , H03F1/26 , H03F3/183 , H03F3/45103 , H03F2200/372 , H03F2203/45492 , H03F2203/45722
摘要： The following invention refers to a low noise amplifier comprising at least one first circuit block (1, Q1-Q4, Q11-Q12) capable of amplifying a first voltage signal (Vin, V(INP)-V(INN)) in input to the amplifier. The first circuit block (1, Q1-Q4, Q11-Q12) has at least one first terminal coupled to a first supply voltage (Vee) by means of first variable resistor means (RE,2) and at least one second terminal coupled with a second supply voltage (Vcc) by means of at least one resistor (Rc, Rc1, Rc2). The at least one second terminal is coupled to the at least one output terminal of the amplifier (OUT, OUTP-OUTN) and said input voltage signal (Vin, V(INP)-V(INN)) is applied to the at least one further terminal (IN, INP-INN) of the first circuit block. The amplifier comprises a feedback network (RF, RF1, RF2) coupled to the output terminal (OUT, OUTP-OUTN) and to the at least one further terminal (IN, INP-INN) of the first circuit block. The amplifier comprises second circuit means (3) placed between the second supply voltage (Vcc) and the at least one further terminal (IN, INP-INN) of the first circuit block and adapted to compensate the variations in value of said first variable resistor means (RE,2) to ensure a substantially constant input resistance (R in ) of the amplifier.
摘要翻译： 以下发明涉及一种低噪声放大器，其包括能够放大第一电压信号（Vin，V（INP）-V（INN））的至少一个第一电路块（1，Q1-Q4，Q11-Q12） 放大器。 第一电路块（1，Q1-Q4，Q11-Q12）具有通过第一可变电阻器装置（RE，2）耦合到第一电源电压（Vee）的至少一个第一端子，以及至少一个与 通过至少一个电阻器（Rc，Rc1，Rc2）的第二电源电压（Vcc）。 至少一个第二端子耦合到放大器的至少一个输出端子（OUT，OUTP-OUTN），并且所述输入电压信号（Vin，V（INP）-V（INN））被施加到所述至少一个 第一电路块的另外的端子（IN，INP-INN）。 放大器包括耦合到输出端子（OUT，OUTP-OUTN）和第一电路块的至少一个另外的端子（IN，INP-INN）的反馈网络（RF，RF1，RF2）。 放大器包括放置在第二电源电压（Vcc）和第一电路块的至少一个另外的端子（IN，INP-INN）之间的第二电路装置（3），并且适于补偿所述第一可变电阻器的值的变化 意味着（RE，2）以确保放大器基本上恒定的输入电阻（R in）。
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