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    RECEIVER COMPRISING AN AMPLIFIER
    2.
    发明公开
    RECEIVER COMPRISING AN AMPLIFIER 审中-公开
    包含放大器的接收器

    公开(公告)号：EP1851854A1

    公开(公告)日：2007-11-07

    申请号：EP06710788.8

    申请日：2006-01-30

    Applicant: NXP B.V.

    Inventor： VAN DER HEIJDEN, Edwin ,  VEENSTRA, Hugo

    IPC: H03H11/32 ,  H03F3/45

    CPC classification number: H03H11/32 ,  H03F1/32 ,  H03F3/45089 ,  H03F3/45103 ,  H03F2200/372 ,  H03F2200/537 ,  H03F2203/45386

    Abstract: The invention relates to a receiver (1) comprising an amplifier (31-34) for amplifying an antenna signal, which amplifier (31-34) comprises an amplifier input (11a) and an amplifier output (12a,12b), the amplifier input (11a) being a single ended input for receiving the antenna signal, the amplifier output (12a, 12b) being a differential output, and the amplifier (31-34) comprising circuit (41,42) for reducing a common mode input impedance of the amplifier (31-34).

    Abstract translation: 本发明涉及包括用于放大天线信号的放大器（31-34）的接收器（1），该放大器（31-34）包括放大器输入（11a）和放大器输出（12a，12b），放大器输入 （11a）是用于接收天线信号的单端输入端，所述放大器输出端（12a，12b）是差分输出端，并且所述放大器（31-34）包括用于降低共模输入阻抗的电路（41,42） 放大器（31-34）。

    n-BIT CONVERTER WITH n-1 MAGNITUDE AMPLIFIERS AND n COMPARATORS
    3.
    发明授权
    n-BIT CONVERTER WITH n-1 MAGNITUDE AMPLIFIERS AND n COMPARATORS 失效
    用n-1的尺寸和放大器N个比较N位转换器

    公开(公告)号：EP0795235B1

    公开(公告)日：2002-11-13

    申请号：EP95940069.8

    申请日：1995-11-29

    Applicant: ANALOG DEVICES, INCORPORATED

    Inventor： MURDEN, Frank ,  MORELAND, Carl, W.

    IPC: H03M1/44 ,  H03F3/45

    CPC classification number: H03F3/26 ,  H03F3/45103 ,  H03F3/45107 ,  H03F2203/45302 ,  H03F2203/45311 ,  H03F2203/45318 ,  H03F2203/45352 ,  H03F2203/45371 ,  H03F2203/45702 ,  H03F2203/45722 ,  H03M1/445

    Abstract: A serial-type A/D converter that uses magnitude amplifiers ('magamps') and comparators for effecting the conversion of analog signals to Gray scale code signals that are then converted to binary digital signals by a Gray scale code-to-binary portion of the serial-type A/D converter. More specifically, a serial-type A/D converter that uses an n-bit converter that has n-1 magamps and n-comparators. The n-1 magamps are cascaded such that the VOL and VOH outputs of a stage is the inputs to the next stage. The output of the comparators are input to the Gray scale code-to-binary portion of the serial A/D converter. The latching of the comparators occurs outside of the magamps. This allows for the parallel latching of the n comparators. The speed of the serial-type A/D converter is determined by the bandwidth of the magamps. The serial-type A/D converter includes an offset method that significantly reduces the effects of early voltage, VA, on the output waveforms. Each stage of the serial-type A/D converter may have any desired gain and not limited to a particular gain.

    n-BIT CONVERTER WITH n-1 MAGNITUDE AMPLIFIERS AND n COMPARATORS
    8.
    发明公开
    n-BIT CONVERTER WITH n-1 MAGNITUDE AMPLIFIERS AND n COMPARATORS 失效
    用n-1的尺寸和放大器N个比较N位转换器

    公开(公告)号：EP0795235A1

    公开(公告)日：1997-09-17

    申请号：EP95940069.0

    申请日：1995-11-29

    Applicant: ANALOG DEVICES, INCORPORATED

    Inventor： MURDEN, Frank ,  MORELAND, Carl, W.

    IPC: H03F3 ,  H03M1

    CPC classification number: H03F3/26 ,  H03F3/45103 ,  H03F3/45107 ,  H03F2203/45302 ,  H03F2203/45311 ,  H03F2203/45318 ,  H03F2203/45352 ,  H03F2203/45371 ,  H03F2203/45702 ,  H03F2203/45722 ,  H03M1/445

    Abstract: A serial-type A/D converter that uses magnitude amplifiers ('magamps') and comparators for effecting the conversion of analog signals to Gray scale code signals that are then converted to binary digital signals by a Gray scale code-to-binary portion of the serial-type A/D converter. More specifically, a serial-type A/D converter that uses an n-bit converter that has n-1 magamps and n-comparators. The n-1 magamps are cascaded such that the VOL and VOH outputs of a stage is the inputs to the next stage. The output of the comparators are input to the Gray scale code-to-binary portion of the serial A/D converter. The latching of the comparators occurs outside of the magamps. This allows for the parallel latching of the n comparators. The speed of the serial-type A/D converter is determined by the bandwidth of the magamps. The serial-type A/D converter includes an offset method that significantly reduces the effects of early voltage, VA, on the output waveforms. Each stage of the serial-type A/D converter may have any desired gain and not limited to a particular gain.

    Volume controller
    9.
    发明公开
    Volume controller 失效
    液位控制。

    公开(公告)号：EP0661804A3

    公开(公告)日：1996-07-17

    申请号：EP94309866.5

    申请日：1994-12-28

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Tagomori, Reiji, c/o In. Prop. Div., Toshiba Corp.

    IPC: H03G1/00 ,  H03G3/00

    CPC classification number: H03F3/45103 ,  H03F2203/45311 ,  H03F2203/45398 ,  H03G1/0088 ,  H03G3/001 ,  H03G5/10 ,  H03G7/06

    Abstract: A volume controllre include a volume regulating circuit having an input terminal connected to an audio signal source and a control terminal to which a volume regulating voltage is supplied, a circuit for supplying parallel data in multiple bits, a D/A conversion circuit having including multiple current circuits formed in parallel corresponding to every bit of the parallel data, for ON/OFF controlling the current circuits according to respective bit data and for supplying total sum current flowing through these current circuits, a control circuit for controlling output current from the D/A conversion circuit to non-linear current by switching current volumes of respective current circuits corresponding to the most significant bit data out of the parallel data, and a circuit for generating the volume regulating voltage by convertine the output current from the D/A conversion circuit into voltage.

    Amplificateur différentiel à couplage capacitif
    10.
    发明公开
    Amplificateur différentiel à couplage capacitif 失效
    Differenzverstärkermit Kondensatorkopplung。

    公开(公告)号：EP0414328A1

    公开(公告)日：1991-02-27

    申请号：EP90202260.7

    申请日：1990-08-22

    Applicant: PHILIPS COMPOSANTS ,  Philips Electronics N.V.

    Inventor： Chevallier, Gilles

    IPC: H03F1/56 ,  H03F3/45

    CPC classification number: H03F3/45103 ,  H03F1/56

    Abstract: La présente invention concerne un amplificateur du type cascode comprenant un étage différentiel comportant un premier (T₁) et un deuxième (T₂) transistor dont les émetteurs sont connectés respectivement à une première (I₁) et une deuxième (I₂) source de courant et sont reliés entre eux par une première résistance (R₁₂) et dont les collecteurs sont connectés à une charge active constituée par le trajet collec­teur-émetteur respectivement d'un troisième (T₃) et d'un qua­trième (T₄) transistor en série respectivement avec une deuxième (R₃) et une troisième (R₄) résistance dont une borne est connectée à une source de tension d'alimentation, les troisièmes (T₃) et quatrième (T₄) transistors ayant leur base connectée à une source de tension de référence, la base des premier (T₁) et deuxième (T₂) transistors étant reliée à tra­vers un premier (C₁) et un deuxième (C′₁) condensateur à un générateur de courant équivalent à une source de courant en parallèle de laquelle est disposée une impédance. Pour amélio­rer le couplage de courant à l'entrée de l'amplificateur dans le cas où ladite impédance est non selfique, il comporte un troisième (C₂) et un quatrième (C′₂) condensateur disposés en série avec respectivement une première (R₅₁) et une deuxième (R₆₁) résistance de contre-réaction de l'amplificateur, entre le générateur de courant et respectivement une première et une deuxième sortie de l'amplificateur.

    Abstract translation: 本发明涉及共源共栅型放大器，其包括具有第一（T1）和第二（T2）晶体管的差分级，其发射极分别连接到第一（I1）和第二（I2）电流源并被连接 通过第一电阻器（R12）彼此连接，并且其集电极连接到由分别与第三（T3）和第四（T4）晶体管的集电极 - 发射极路径组成的有源负载，分别与第二（R3）和 第三（R4）电阻器，其端子连接到电源电压源，第三（T3）和第四（T4）晶体管的基极连接到参考电压源，第一（T1）和第二 T2）晶体管通过第一（C1）和第二（C'1）电容器连接到等效于电流源的电流发生器并联布置有阻抗。 为了在所述阻抗没有自感的情况下改善放大器输入处的电流耦合，它包括分别与第一（R51）和第二（R51）电容串联布置的第三（C2）和第四（C'2）电容器 放大器的第二（R61）反馈电阻器，分别位于电流发生器和放大器的第一和第二输出端之间。 ... ...

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