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    APPARATUSES AND METHODS FOR BI-DIRECTIONAL ACCESS OF CROSS-POINT ARRAYS
    2.
    发明公开
    APPARATUSES AND METHODS FOR BI-DIRECTIONAL ACCESS OF CROSS-POINT ARRAYS 审中-公开

    公开(公告)号：EP3140834A4

    公开(公告)日：2018-01-03

    申请号：EP15788992

    申请日：2015-05-04

    申请人： MICRON TECHNOLOGY INC

    发明人： CASTRO HERNAN A

    IPC分类号： G11C13/00

    CPC分类号： G11C13/003 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/76

    摘要： The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of accessing memory cells in a cross point memory array. In one aspect, an apparatus comprises a memory array. The apparatus further comprises a memory controller configured to cause an access operation, where the access operation includes application of a first bias across a memory cell of the memory array for a selection phase of the access operation and application of a second bias, lower in magnitude than the first bias, across the memory cell for an access phase of the access operation. The memory controller is further configured to cause a direction of current flowing through the memory cell to be reversed between the selection phase and the access phase.

    APPARATUSES AND METHODS FOR BI-DIRECTIONAL ACCESS OF CROSS-POINT ARRAYS
    4.
    发明公开
    APPARATUSES AND METHODS FOR BI-DIRECTIONAL ACCESS OF CROSS-POINT ARRAYS 审中-公开
    VORRICHTUNGEN UND VERFAHRENFÜRBIDIREKTIONALEN ZUGANG VON KREUZPUNKTARRAYS

    公开(公告)号：EP3140834A1

    公开(公告)日：2017-03-15

    申请号：EP15788992.4

    申请日：2015-05-04

    申请人： Micron Technology, Inc.

    发明人： CASTRO, Hernan A.

    IPC分类号： G11C13/00

    CPC分类号： G11C13/003 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/76

    摘要： The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of accessing memory cells in a cross point memory array. In one aspect, an apparatus comprises a memory array. The apparatus further comprises a memory controller configured to cause an access operation, where the access operation includes application of a first bias across a memory cell of the memory array for a selection phase of the access operation and application of a second bias, lower in magnitude than the first bias, across the memory cell for an access phase of the access operation. The memory controller is further configured to cause a direction of current flowing through the memory cell to be reversed between the selection phase and the access phase.

    摘要翻译： 所公开的技术通常涉及其操作的装置和方法，更具体地涉及交叉点存储器阵列和访问交叉点存储器阵列中的存储器单元的方法。 一方面，一种装置包括存储器阵列。 该设备还包括存储器控制器，其被配置为引起访问操作，其中访问操作包括跨越存储器阵列的存储器单元施加第一偏置，用于存取操作的选择阶段和应用较低幅度的第二偏置 比第一偏置，跨越存储单元访问操作的访问阶段。 存储器控制器还被配置为使得流过存储器单元的电流的方向在选择阶段和访问阶段之间反转。

    Memory cell with trigger element
    7.
    发明公开
    Memory cell with trigger element 审中-公开
    Speicherzelle mit Triggerelement

    公开(公告)号：EP1927992A1

    公开(公告)日：2008-06-04

    申请号：EP07023074.3

    申请日：2007-11-28

    申请人： Qimonda North America Corp.

    发明人： Philipp, Jan Boris ,  Happ, Thomas, Dr. ,  Nirschl, Thomas

    IPC分类号： G11C16/02

    CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C2213/76

    摘要： A memory device includes a plurality of word lines extending as rows and bit lines extending as columns. A memory cell is coupled between a word line and a bit line, wherein the memory cell includes a unipolar memory element selectively coupled to the bit line via a trigger element.

    摘要翻译： 存储器件包括作为列延伸的行和位线延伸的多个字线。 存储单元耦合在字线和位线之间，其中存储单元包括通过触发元件选择性地耦合到位线的单极存储器元件。