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Patent Agency Ranking
公开(公告)号：EP3761236A2
公开(公告)日：2021-01-06
申请号：EP20178074.9
申请日：2020-06-03
Inventor： CHAWLA, Nitin , ROY, Tanmoy , GROVER, Anuj , DESOLI, Giuseppe
Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.
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公开(公告)号：EP3761236A3
公开(公告)日：2021-05-19
申请号：EP20178074.9
申请日：2020-06-03
Inventor： CHAWLA, Nitin , ROY, Tanmoy , GROVER, Anuj , DESOLI, Giuseppe
IPC: G06N3/063 , G11C7/10 , G11C11/54 , G06F17/10 , G06F7/509 , G06F7/544 , G06N3/04 , G06N3/08 , G06G7/16
Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.
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公开(公告)号：EP3796320A2
公开(公告)日：2021-03-24
申请号：EP20192400.8
申请日：2020-08-24
Applicant: STMicroelectronics International N.V.
Inventor： GROVER, Anuj , ROY, Tanmoy
IPC: G11C11/54 , G11C11/412 , G11C7/10 , G11C8/16
Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.
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公开(公告)号：EP3855443A1
公开(公告)日：2021-07-28
申请号：EP21153704.8
申请日：2021-01-27
Applicant: STMicroelectronics International N.V.
Inventor： ROY, Tanmoy , GROVER, Anuj
Abstract: A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values. The stored data values may be stored in an in-memory compute cluster of the memory array, such that operations on the stored data values include combining the multiple data values of the in-memory compute cluster with at least a portion of the generated calibration information as at least part of an in-memory compute operation for the in-memory compute cluster.
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公开(公告)号：EP3796320A3
公开(公告)日：2021-07-21
申请号：EP20192400.8
申请日：2020-08-24
Applicant: STMicroelectronics International N.V.
Inventor： GROVER, Anuj , ROY, Tanmoy
IPC: G11C11/54 , G11C11/412 , G11C7/10 , G11C8/16
Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.
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