公开(公告)号：EP3836144A1

公开(公告)日：2021-06-16

申请号：EP20212102.6

申请日：2020-12-07

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： CHAWLA, Nitin ,  GROVER, Anuj ,  DESOLI, Giuseppe ,  DHORI, Kedar Janardan ,  BOESCH, Thomas ,  KUMAR, Promod

IPC: G11C11/417 ,  G11C5/14

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.

公开(公告)号：EP3798853A3

公开(公告)日：2021-06-16

申请号：EP20194994.8

申请日：2020-09-08

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： CHAWLA, Nitin ,  DESOLI, Giuseppe ,  GROVER, Anuj ,  BOESCH, Thomas ,  SINGH, Surinder Pal ,  AYODHYAWASI, Manuj

IPC: G06F12/02 ,  G06N3/063

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

公开(公告)号：EP3761236A2

公开(公告)日：2021-01-06

申请号：EP20178074.9

申请日：2020-06-03

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： CHAWLA, Nitin ,  ROY, Tanmoy ,  GROVER, Anuj ,  DESOLI, Giuseppe

IPC: G06N3/063 ,  G11C7/10 ,  G11C11/54 ,  G06F17/10 ,  G06F7/509 ,  G06F7/544 ,  G06N3/04

Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.

公开(公告)号：EP3761236A3

公开(公告)日：2021-05-19

申请号：EP20178074.9

申请日：2020-06-03

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： CHAWLA, Nitin ,  ROY, Tanmoy ,  GROVER, Anuj ,  DESOLI, Giuseppe

IPC: G06N3/063 ,  G11C7/10 ,  G11C11/54 ,  G06F17/10 ,  G06F7/509 ,  G06F7/544 ,  G06N3/04 ,  G06N3/08 ,  G06G7/16

Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.

公开(公告)号：EP3859535A1

公开(公告)日：2021-08-04

申请号：EP21153708.9

申请日：2021-01-27

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： CHAWLA, Nitin ,  BOESCH, Thomas ,  GROVER, Anuj ,  SINGH, Surinder Pal ,  DESOLI, Giuseppe

IPC: G06F12/02 ,  G11C11/22 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/419 ,  G11C7/10 ,  G11C8/04 ,  G11C8/08 ,  G11C8/10 ,  G11C11/54 ,  G06N3/04 ,  G06N3/063

Abstract: A system includes a random access memory organized into indivudally addressable words. Streaming access control circuitry is coupled to word lines of the random access memory. The streaming access control circuitry responds to a request to access a plurality of individually addressable words of a determined region of the random access memory by generating control signals to drive the word lines to streamingly access the plurality of individually addressable words of the determined region. The request indicates an offset associated with the determined region and a pattern associated with the streaming access.

公开(公告)号：EP3822737A3

公开(公告)日：2021-07-07

申请号：EP20196625.6

申请日：2020-09-17

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： CHAWLA, Nitin

IPC: G06F1/04 ,  G06F1/32

Abstract: Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.

公开(公告)号：EP3822737A2

公开(公告)日：2021-05-19

申请号：EP20196625.6

申请日：2020-09-17

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： CHAWLA, Nitin

IPC: G06F1/04 ,  G06F1/32

Abstract: Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.

公开(公告)号：EP3798853A2

公开(公告)日：2021-03-31

申请号：EP20194994.8

申请日：2020-09-08

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： CHAWLA, Nitin ,  DESOLI, Giuseppe ,  GROVER, Anuj ,  BOESCH, Thomas ,  SINGH, Surinder Pal ,  AYODHYAWASI, Manuj

IPC: G06F12/02 ,  G06N3/063

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

公开(公告)号：EP4293671A1

公开(公告)日：2023-12-20

申请号：EP23174857.5

申请日：2023-05-23

Applicant: STMicroelectronics International N.V.

Inventor： RAWAT, Harsh ,  DHORI, Kedar Janardan ,  KUMAR, Promod ,  CHAWLA, Nitin ,  AYODHYAWASI, Manuj

IPC: G11C7/10 ,  G06N3/063 ,  G11C7/12

Abstract: An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by local bit lines. A row controller circuit selectively actuates one word line per sub-array for an in-memory compute operation. A global bit line is capacitively coupled to many local bit lines in either a column direction or row direction. An analog global output voltage on each global bit line is an average of local bit line voltages on the capacitively coupled local bit lines. The analog global output voltage is sampled and converted by an analog-to-digital converter (ADC) circuit to generate a digital decision signal output for the in-memory compute operation.

公开(公告)号：EP4160598A1

公开(公告)日：2023-04-05

申请号：EP22199291.0

申请日：2022-09-30

Applicant: STMicroelectronics International N.V.

Inventor： RAWAT, Harsh ,  DHORI, Kedar Janardan ,  KUMAR, Promod ,  CHAWLA, Nitin ,  AYODHYAWASI, Manuj

IPC: G11C7/10 ,  G06N3/063 ,  G11C11/412 ,  G11C11/54

Abstract: A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.