公开(公告)号：EP3255669A1

公开(公告)日：2017-12-13

申请号：EP17175078.9

申请日：2017-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： BAE, Ki Cheol ,  PARK, Chul Woo ,  LEE, Kwang Sub ,  LEE, Sang Gyun ,  JANG, Se Young ,  CHO, Chi Hyun

IPC: H01L23/64 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L23/645 ,  H01L23/3128 ,  H01L23/642 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L28/40 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83851 ,  H01L2224/92247 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30101 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor assembly with a package on package (POP) structure includes a first semiconductor package (100) having a first lower substrate (110), a first upper substrate (120) facing the first lower substrate, and a first semiconductor chip (130) mounted on an area of the first lower substrate. The POP structure further includes a second semiconductor package (200) having a second lower substrate (210) stacked on the first semiconductor package and spaced apart from the first semiconductor package, and a second semiconductor chip (220) mounted in an area of the second lower substrate. At least one passive element (301) is disposed in at least one of the first semiconductor package and the second semiconductor package and electrically connected to the second semiconductor chip.

Abstract translation: 具有堆叠式封装（POP）结构的半导体组件包括具有第一下基板（110），面对第一下基板的第一上基板（120）和第一半导体芯片（130）的第一半导体封装件（100） 安装在第一下基板的区域上。 POP结构还包括具有堆叠在第一半导体封装上并与第一半导体封装分隔开的第二下基板（210）的第二半导体封装（200）以及安装在第二半导体封装（200）的区域中的第二半导体芯片（220） 下基板。 至少一个无源元件（301）设置在第一半导体封装和第二半导体封装中的至少一个中并且电连接到第二半导体芯片。