公开(公告)号：EP3410483A1

公开(公告)日：2018-12-05

申请号：EP18175313.8

申请日：2018-05-31

申请人： FRAUNHOFER-GESELLSCHAFT zur Förderung der angewandten Forschung e.V.

发明人： Böttcher, Mathias ,  Wolf, M. Jürgen

IPC分类号： H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/98 ,  H01L25/10

CPC分类号： H01L25/065 ,  H01L21/568 ,  H01L23/49833 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/1533 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/85

摘要： Die Anmeldung betrifft ein Verfahren zur Herstellung eines Packages (1). Bei dem vorgeschlagenen Verfahren werden zunächst eine erste Bauteilanordnung (2) und eine zweite Bauteilanordnung (13) bereitgestellt. Die erste Bauteilanordnung (2) und die zweite Bauteilanordnung (13) weisen jeweils eine flächige Umverdrahtungslage (6, 16) und jeweils zumindest eine auf einer in Richtung einer Vorderseite der Bauteilanordnung (2, 13) weisenden Seite der Umverdrahtungslage (6, 16) angeordnete elektronische Komponente auf (11, 11', 17). Die Umverdrahtungslage (6, 16) weist elektrisch isolierendes Material (8) und Leiterbahnen (9, 9') auf. Zumindest eine der Leiterbahnen (9, 9') der Umverdrahtungslage (6, 16) ist mit der elektronischen Komponente (11, 11', 17) elektrisch leitend verbunden. In einem weiteren Schritt werden die Bauteilanordnungen (2, 13) derart zueinander angeordnet, dass die Vorderseiten der Bauteilanordnungen (2, 13) einander zugewandt sind und dass ein durch die Bauteilanordnungen (2, 13) begrenzter Zwischenraum (21) zwischen den Umverdrahtungslagen (6, 16) ausgebildet wird. In typischen Ausführungen wird ein Füllmaterial in den Zwischenraum eingebracht.

公开(公告)号：EP3289609A1

公开(公告)日：2018-03-07

申请号：EP16723581.1

申请日：2016-04-28

申请人： Qualcomm Incorporated

发明人： KIM, Chin-Kwan ,  KUMAR, Rajneesh ,  NOVESKI, Vladimir ,  FU, Jie ,  SYED, Ahmer Raza ,  SHAH, Milind Pravin ,  BCHIR, Omar James

IPC分类号： H01L23/16 ,  H01L25/10 ,  H01L23/538 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

摘要： Some features pertain to a package that includes a redistribution portion, a first die coupled to the redistribution portion, a core layer coupled to the redistribution portion, and an encapsulation layer encapsulating the first die and the core layer. The redistribution portion includes a first dielectric layer. The core layer has a higher Young's Modulus than the encapsulation layer. In some implementations, the core layer includes a glass fiber (e.g., core layer is a glass reinforced dielectric layer). In some implementations, the core layer has a Young's Modulus of about at least 15 gigapascals (Gpa). In some implementations, the first die includes a front side and a back side, where the front side of the first die is coupled to the redistribution portion. In some implementations, the first dielectric layer is a photo imageable dielectric (PID) layer.

公开(公告)号：EP3255669A1

公开(公告)日：2017-12-13

申请号：EP17175078.9

申请日：2017-06-08

申请人： Samsung Electronics Co., Ltd.

发明人： BAE, Ki Cheol ,  PARK, Chul Woo ,  LEE, Kwang Sub ,  LEE, Sang Gyun ,  JANG, Se Young ,  CHO, Chi Hyun

IPC分类号： H01L23/64 ,  H01L25/10 ,  H01L25/16

CPC分类号： H01L23/645 ,  H01L23/3128 ,  H01L23/642 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L28/40 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83851 ,  H01L2224/92247 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30101 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor assembly with a package on package (POP) structure includes a first semiconductor package (100) having a first lower substrate (110), a first upper substrate (120) facing the first lower substrate, and a first semiconductor chip (130) mounted on an area of the first lower substrate. The POP structure further includes a second semiconductor package (200) having a second lower substrate (210) stacked on the first semiconductor package and spaced apart from the first semiconductor package, and a second semiconductor chip (220) mounted in an area of the second lower substrate. At least one passive element (301) is disposed in at least one of the first semiconductor package and the second semiconductor package and electrically connected to the second semiconductor chip.

摘要翻译： 具有堆叠式封装（POP）结构的半导体组件包括具有第一下基板（110），面对第一下基板的第一上基板（120）和第一半导体芯片（130）的第一半导体封装件（100） 安装在第一下基板的区域上。 POP结构还包括具有堆叠在第一半导体封装上并与第一半导体封装分隔开的第二下基板（210）的第二半导体封装（200）以及安装在第二半导体封装（200）的区域中的第二半导体芯片（220） 下基板。 至少一个无源元件（301）设置在第一半导体封装和第二半导体封装中的至少一个中并且电连接到第二半导体芯片。

公开(公告)号：EP3140861A1

公开(公告)日：2017-03-15

申请号：EP15723397.4

申请日：2015-05-05

申请人： Qualcomm Incorporated

发明人： WE, Hong Bok ,  KIM, Dong Wook ,  LEE, Jae Sik ,  GU, Shiqun ,  RADOJCIC, Ratibor

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

CPC分类号： H01L23/49827 ,  H01L21/31127 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81484 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/20648 ,  H01L2924/3511 ,  H05K1/09 ,  H05K1/115 ,  H05K2201/09563 ,  H01L2924/014 ,  H01L2224/81

摘要： A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate and a plurality of filled vias through the substrate. The substrate block may be used to manufacture package substrates, and these package substrate may be incorporated into a PoP structure. The package substrate includes a carrier having a plurality of vertical interconnections and a bar coupled to the vertical interconnections.

摘要翻译： 提供了具有增加的宽度的衬底块。 衬底块包括两个衬底条，并且衬底条各自包括衬底和穿过衬底的多个填充的通孔。 衬底块可用于制造封装衬底，并且这些封装衬底可以并入PoP结构中。 封装衬底包括具有多个垂直互连的载体和耦合到垂直互连的条。

公开(公告)号：EP3104409A2

公开(公告)日：2016-12-14

申请号：EP16166593.0

申请日：2016-04-22

申请人： MediaTek, Inc

发明人： LIN, Tzu-Hung ,  PENG, I-Hsuan ,  HSIAO, Ching-Wen

IPC分类号： H01L23/538 ,  H01L25/16 ,  H01L25/10 ,  H01L21/60 ,  H01L21/56

CPC分类号： H01L25/16 ,  H01L21/568 ,  H01L21/78 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16145 ,  H01L2224/16265 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81815 ,  H01L2224/92124 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

摘要： A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor package. The semiconductor package includes a semiconductor die (100). A redistribution layer (RDL) structure (230) is disposed on the semiconductor die and is electrically connected to the semiconductor die. An active (140) or passive element (150) is disposed between the semiconductor die and the RDL structure. A molding compound (220) surrounds the semiconductor die and the active or passive element.

摘要翻译： 提供半导体封装组件。 该半导体封装组件包括半导体封装。 该半导体封装包括半导体管芯（100）。 再分布层（RDL）结构（230）设置在半导体管芯上并电连接到半导体管芯。 有源（140）或无源元件（150）设置在半导体管芯和RDL结构之间。 模塑料（220）围绕半导体管芯和有源或无源元件。

公开(公告)号：EP3091573A2

公开(公告)日：2016-11-09

申请号：EP16161852.5

申请日：2016-03-23

申请人： MediaTek, Inc

发明人： HSIAO, Ching-Wen ,  LIN, Tzu-Hung ,  PENG, I-Hsuan ,  HSIEH, Tung-Hsien ,  CHANG, Sheng-Ming

IPC分类号： H01L25/16 ,  H01L25/10 ,  H01L23/538 ,  H01L23/34 ,  H01L23/50

CPC分类号： H01L23/3675 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor chip package assembly (1) includes a package substrate (200) having a chip mounting surface (200a); a plurality of solder pads (212) disposed on the chip mounting surface; a first dummy pad (211) and a second dummy pad (211) spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask (202) on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package (100) mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls (250) on respective said solder pads (212); a discrete device (150)having a first terminal (151) and a second terminal (152) disposed between the chip package and the package substrate; a first solder (154) connecting the first terminal with the first dummy pad (211) and the chip package (100); and a second solder (154) connecting the second terminal (152) with the second dummy pad (211) and the chip package (100).

摘要翻译： 半导体芯片封装组件（1）包括具有芯片安装表面（200a）的封装衬底（200）; 设置在所述芯片安装表面上的多个焊盘（212）; 与设置在芯片安装表面上的第一虚拟焊盘间隔开的第一虚拟焊盘（211）和第二虚拟焊盘（211）; 在芯片安装表面上的焊接掩模（202），并且部分地覆盖焊盘，第一虚拟焊盘和第二虚拟焊盘; 芯片封装（100），其安装在所述芯片安装表面上并且通过在所述焊盘（212）上的多个焊球（250）电连接到所述封装基板; 具有设置在所述芯片封装和所述封装基板之间的第一端子（151）和第二端子（152）的分立器件（150） 将第一端子与第一虚拟焊盘（211）和芯片封装（100）连接的第一焊料（154）; 以及将第二端子（152）与第二虚拟焊盘（211）和芯片封装（100）连接的第二焊料（154）。

公开(公告)号：EP3065175A1

公开(公告)日：2016-09-07

申请号：EP16153542.2

申请日：2016-01-31

申请人： MediaTek, Inc

发明人： LIN, Tzu-Hung ,  PENG, I-Hsuan

IPC分类号： H01L25/10 ,  H01L25/16 ,  H01L25/065

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/04042 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package (500a) including a first semiconductor die (302). A first molding compound (350) surrounds the first semiconductor die. A first redistribution layer (RDL) structure (308) is disposed on a bottom surface of the first molding compound. The first semiconductor die is coupled to the first RDL structure. A second redistribution layer (RDL) structure (328) is disposed on a top surface of the first molding compound. A passive device (330) is coupled to the second RDL structure.

摘要翻译： 本发明提供一种半导体封装组件。 半导体封装组件包括包括第一半导体管芯（302）的第一半导体封装（500a）。 第一模塑料（350）围绕第一半导体管芯。 第一再分配层（RDL）结构（308）设置在第一模塑料的底表面上。 第一半导体管芯耦合到第一RDL结构。 第二再分布层（RDL）结构（328）设置在第一模塑料的顶表面上。 无源器件（330）耦合到第二RDL结构。

公开(公告)号：EP2605279A1

公开(公告)日：2013-06-19

申请号：EP12005904.3

申请日：2012-08-16

申请人： Broadcom Corporation

发明人： Hu, Kevin ,  Zhao, Sam ,  Khan, Rezaur ,  Vorenkamp, Pieter ,  Karikalan, Sampath ,  Chen, Xiangdong

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L25/105 ,  H01L21/50 ,  H01L21/78 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/2919 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/821 ,  H01L2224/83 ,  H01L2224/9202 ,  H01L2224/92133 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The top die and the bottom die are insulated from one another by an insulation arrangement. The top die and the bottom die are also interconnected through the insulation arrangement. The insulation arrangement can include a top molding compound that flanks the top die and a bottom molding compound that flanks the bottom die. The top die and the bottom die can be interconnected through at least the top molding compound. Furthermore, the top die and the bottom die can be interconnected through a conductive via that extends within the insulation arrangement.

摘要翻译： 本公开的示例性实施方案包括具有来自位于底部复原晶片的底模上方的顶部重构晶片的顶模的堆叠封装。 顶部模具和底部模具通过绝缘装置彼此绝缘。 顶模和底模也通过绝缘装置互连。 绝缘装置可以包括位于顶模侧面的顶部模塑料和位于底模侧面的底部模塑料。 顶模和底模可以通过至少顶部模塑料相互连接。 此外，顶模和底模可以通过在绝缘装置内延伸的导电通孔互连。

公开(公告)号：EP2596530A2

公开(公告)日：2013-05-29

申请号：EP11741499.5

申请日：2011-07-18

申请人： Tessera, Inc.

发明人： HABA, Belgacem

IPC分类号： H01L23/52 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/8385 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/83851 ,  H01L2224/45099

摘要： A microelectronic package (290) having a (substrate 230), a microelectronic element (170), e.g., a chip, and terminals (240) can have conductive elements (238) electrically connected with element contacts of the chip and contacts of the substrate. Conductive elements can be electrically insulated from one another for simultaneously carrying different electric potentials. An encapsulant (201) can overlie the first surface (136) of the substrate and at least a portion of a face (672) of the microelectronic element remote from the substrate, and may have a major surface (200) above the microelectronic element. A plurality of package contacts (120, 220, 408, 410, 427) can overlie a face (672) of the microelectronic element remote from the substrate. The package contacts, e.g., conductive masses (410), substantially rigid posts (120, 220), can be electrically interconnected with terminals (240) of the substrate (230), such as through the conductive elements. The package contacts can have top surfaces (121) at least partially exposed at the major (surface 200) of the encapsulant (201).

公开(公告)号：EP2330621A1

公开(公告)日：2011-06-08

申请号：EP10014069.8

申请日：2010-10-28

申请人： MStar Semiconductor, Inc

发明人： Yang, Chih-An ,  Pan, Yi-Hsiang ,  Chang, Ming-Chung ,  Chang, Chu-Chia ,  Chang, Chih-Hao ,  Hsu, Wei-Lun

IPC分类号： H01L21/98 ,  H01L25/10 ,  H01L25/16 ,  H01L25/18 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L25/105 ,  H01L23/3107 ,  H01L23/49531 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00015

摘要： A package on package stacking method is provided. The package on package stacking method includes attaching a lead frame (24) and a substrate (22); attaching an integrated circuit (IC, 34) and the substrate, and electrically connecting the IC (34) and the lead frame (24); and packaging the IC (34), a part of the substrate (22) and a part of the lead frame (24), and exposing a surface mount joint to form a concave package (42).

摘要翻译： 提供了一种封装堆叠方法。 封装堆叠方法包括附接引线框架（24）和基板（22）; 连接集成电路（IC，34）和基板，并且电连接IC（34）和引线框架（24）; 以及封装所述IC（34），所述基板（22）的一部分和所述引线框架（24）的一部分，并且暴露表面安装接头以形成凹形封装（42）。