公开(公告)号：EP2362417B1

公开(公告)日：2018-01-10

申请号：EP11004204.1

申请日：2009-09-02

申请人： Linear Technology Corporation

发明人： Pruitt, David, A.

IPC分类号： H01L23/64 ,  H01L23/495 ,  H01F19/08

CPC分类号： H01F19/08 ,  H01F38/14 ,  H01F2019/085 ,  H01F2027/2814 ,  H01L23/48 ,  H01L23/4952 ,  H01L23/642 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/072 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/4823 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48491 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/49052 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/4943 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/48824

摘要： A semiconductor device is configured to provide current and voltage isolation inside an integrated circuit package. The semiconductor device includes first and second semiconductor dies, a first isolating block positioned on the first semiconductor die, and a second isolating block positioned on the second semiconductor die. The semiconductor device also includes a first interconnect coil having a plurality of wires connecting the first semiconductor die to the second isolating block, and a second interconnect coil having a plurality of wires connecting the second semiconductor die to the first isolating block.

公开(公告)号：EP3151273A1

公开(公告)日：2017-04-05

申请号：EP16194094.5

申请日：2014-12-03

申请人： NXP USA, Inc.

发明人： SZYMANOWSKI, Margaret A. ,  MUSA, Sarmad K ,  SANTOS, Fernando A ,  SHAH, Mahesh K.

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H03F1/0288 ,  H01L21/4821 ,  H01L23/3121 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/552 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03F3/195 ,  H03F3/211 ,  H03F3/213 ,  H03F2200/451 ,  H03F2203/21106 ,  H01L2924/00 ,  H01L2224/45099

摘要： A system and method for packaging a semiconductor device (20) that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate (74) on which a first circuit (22) and a second circuit (24) are formed proximate to each other. An isolation wall (50) of electrically conductive material is located between the first circuit and the second circuit, the isolation wall (50) being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. The isolation wall (50) includes a plurality of holes (52) through which encapsulation material may flow during a process of making the semiconductor device (10). Several types of isolation wall (50) are presented.

摘要翻译： 提出了一种用于封装包括壁以减少电磁耦合的半导体器件（20）的系统和方法。 半导体器件具有基板（74），第一电路（22）和第二电路（24）彼此靠近地形成在其上。 导电材料的隔离壁（50）位于第一电路和第二电路之间，隔离壁（50）构造成在半导体器件的操作期间减小第一和第二电路之间的电感耦合。 隔离壁（50）包括多个孔（52），在制造半导体器件（10）的过程中，封装材料可以通过该孔（52）流动。 提出了几种类型的隔离墙（50）。

公开(公告)号：EP2965331A1

公开(公告)日：2016-01-13

申请号：EP14712974.6

申请日：2014-03-07

申请人： Microchip Technology Incorporated

发明人： DIX, Gregory ,  YACH, Randy

IPC分类号： H01G4/40

CPC分类号： H01L28/40 ,  H01G4/06 ,  H01G4/40 ,  H01L23/642 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/0603 ,  H01L2224/06135 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/48265 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/3011 ,  H03K17/689 ,  H04L25/0266 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： At least one high voltage rated isolation capacitor is formed on a face of a primary integrated circuit die. The isolation capacitor AC couples the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitor DC isolates the primary integrated circuit from the second integrated circuit die.

摘要翻译： 至少一个高电压电容器额定隔离形成于表面上的主集成电路，该集成电路的。 隔离电容器AC耦合在第一电压域的第二集成电路中的第二电压域的主集成电路。 隔离电容器DC隔离的第二集成电路，所述初级集成电路。

公开(公告)号：EP2933837A1

公开(公告)日：2015-10-21

申请号：EP15157027.2

申请日：2015-02-27

申请人： Kabushiki Kaisha Toshiba

发明人： Takagi, Kazutaka

IPC分类号： H01L27/08 ,  H01G4/38 ,  H01L49/02 ,  H01L23/66

CPC分类号： H01G4/385 ,  H01L23/66 ,  H01L27/0805 ,  H01L28/60 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2224/48195 ,  H01L2224/49175 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H03K5/13

摘要： Disclosed is a parallel capacitor comprising an insulating substrate (12), upper electrodes (11e,c), and a lower electrode (14). The upper electrodes are provided in an upper electrode region on a surface of the substrate, including a center portion (12c) and two end portions (12e). The lower electrode is provided on an entire surface of a lower electrode region including a region corresponding to the upper electrode region of an underside of the substrate, the lower electrode region being wider than the region. The capacitance of each capacitor on both ends, configured by the upper electrodes (11e) arranged in the end portions (12e), the lower electrode, and the substrate is smaller than the capacitance of a capacitor in a center portion, configured by the upper electrode (11c) arranged in the center portion (12c) of the substrate, the lower electrode, and the substrate.

摘要翻译： 公开了一种并联电容器，其包括绝缘基板（12），上电极（11e，c）和下电极（14）。 上电极设置在基板的表面上的上电极区域中，包括中心部分（12c）和两个端部（12e）。 下部电极设置在包括与基板的下侧的上部电极区域对应的区域的下部电极区域的整个表面上，下部电极区域比该区域宽。 由配置在端部（12e），下部电极和基板的上部电极（11e）构成的两端的各电容器的电容小于中央部的电容器的电容，由上部 布置在基板的中心部分（12c）中的电极（11c），下电极和基板。

公开(公告)号：EP2819161A3

公开(公告)日：2015-05-06

申请号：EP14158158.7

申请日：2014-03-06

申请人： Kabushiki Kaisha Toshiba

发明人： Ikeda, Kentaro

IPC分类号： H01L23/495

CPC分类号： H01L27/0629 ,  H01L23/492 ,  H01L23/495 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/62 ,  H01L24/73 ,  H01L25/18 ,  H01L29/7786 ,  H01L29/866 ,  H01L29/872 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor device according to one embodiment is provided with a first metal substrate, a second metal substrate separated from the first metal substrate, a normally-off transistor of a silicon semiconductor provided on the first metal substrate, and a normally-on transistor of a nitride semiconductor provided on the second metal substrate.

摘要翻译： 根据一个实施例的半导体器件设置有第一金属基板，与第一金属基板分离的第二金属基板，设置在第一金属基板上的硅半导体的常关晶体管和 提供在第二金属基板上的氮化物半导体。

公开(公告)号：EP1397836B1

公开(公告)日：2014-12-31

申请号：EP02737335.6

申请日：2002-05-30

申请人： ViaSat, Inc.

发明人： BUER, Kenneth, V.

IPC分类号： H01L23/50 ,  H01L23/00 ,  H03F3/195 ,  H01L23/66

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/665 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/49 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01049 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/30111 ,  H03F3/195 ,  H03F2200/12 ,  H01L2924/00014 ,  H01L2924/20643 ,  H01L2924/20653 ,  H01L2924/20654 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2224/48744

公开(公告)号：EP2458636A1

公开(公告)日：2012-05-30

申请号：EP10192922.2

申请日：2010-11-29

申请人： NXP B.V.

发明人： Tiemeijer, Lukas Frederik ,  Cuoco, Vittorio ,  Heeres, Rob Mathijs ,  Van Steenwijk, Anne ,  Willemsen, Marnix Bernard ,  Van der Zanden, Josephus Henricus Bartholomeus

IPC分类号： H01L23/66 ,  H01L29/78 ,  H01L23/522 ,  H01L23/00

CPC分类号： H01L23/66 ,  H01L23/5223 ,  H01L23/642 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/19051 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2224/45099 ,  H01L2924/00

摘要： A compensation network for a radiofrequency (RF) transistor is disclosed. The compensation network comprises first (12, 13) and second (11, 14) bonding bars for coupling to a first terminal of the RF transistor and a compensation capacitor (16, 17) respectively; one or more bond wires coupling the first (12, 13) and second (11, 14) bonding bars together; and a compensation capacitor (16, 17) formed from a first set of conductive elements (16a, 17a) coupled to the second bonding bar(11, 14), the first set of conductive elements (16a, 17a) interdigitating with a second set of conductive elements (16b, 17b) coupled to a second terminal of the RF transistor.

摘要翻译： 公开了一种用于射频（RF）晶体管的补偿网络。 补偿网络包括用于分别耦合到RF晶体管的第一端子和补偿电容器（16,17）的第一（12,13）和第二（11,14）接合棒; 将第一（12,13）和第二（11,14）接合棒结合在一起的一个或多个接合线; 以及由耦合到所述第二接合棒（11,14）的第一组导电元件（16a，17a）形成的补偿电容器（16,17），所述第一组导电元件（16a，17a）与第二组 的耦合到RF晶体管的第二端子的导电元件（16b，17b）。

公开(公告)号：EP2357667A3

公开(公告)日：2012-01-04

申请号：EP10195305.7

申请日：2010-12-16

申请人： NXP B.V.

发明人： Besling, Willem ,  Bakkeer, Theodorus Wilhelmus ,  Lamy, Yann ,  Kochupurackai, Jinesh ,  Roozeboom, Freddy

IPC分类号： H01L23/64 ,  H01L23/66 ,  H01L21/02

CPC分类号： H01L23/66 ,  H01L23/642 ,  H01L24/48 ,  H01L24/49 ,  H01L28/92 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2224/05599 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A variety of circuits, methods and devices are implemented for radiofrequency amplifiers. According to one such implementation, a radiofrequency amplifier circuit is implemented in a SMD package. The circuit amplifies a radiofrequency signal having a base-band portion and a plurality of carrier signals frequency-spaced larger than the base-band bandwidth. The circuit includes a radiofrequency transistor connected to a circuit output having a parasitic output capacitance. The source-drain terminal is electrically connected to the circuit output. An internal shunt inductor provides compensation for the parasitic output capacitance. A high-density capacitor is connected between the internal shunt inductor and a circuit ground. The high-density capacitor has a terminal with a surface area can be at least ten times that of a corresponding planar surface.

公开(公告)号：EP2159841A3

公开(公告)日：2011-04-27

申请号：EP09169228.5

申请日：2009-09-02

申请人： Linear Technology Corporation

发明人： Pruitt, David A.

IPC分类号： H01L25/07 ,  H01L23/64 ,  H01L23/495

CPC分类号： H01F19/08 ,  H01F38/14 ,  H01F2019/085 ,  H01F2027/2814 ,  H01L23/48 ,  H01L23/4952 ,  H01L23/642 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/072 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/4823 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48491 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/49052 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/4943 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/48824

摘要： A semiconductor device is configured to provide current and voltage isolation inside an integrated circuit package. The semiconductor device includes first and second semiconductor dies, a first isolating block positioned on the first semiconductor die, and a second isolating block positioned on the second semiconductor die. The semiconductor device also includes a first interconnect coil having a plurality of wires connecting the first semiconductor die to the second isolating block, and a second interconnect coil having a plurality of wires connecting the second semiconductor die to the first isolating block.

摘要翻译： 半导体器件被配置为在集成电路封装内部提供电流和电压隔离。 该半导体器件包括第一和第二半导体管芯，位于第一半导体管芯上的第一隔离块以及位于第二半导体管芯上的第二隔离块。 该半导体器件还包括具有将第一半导体管芯连接到第二隔离块的多根导线的第一互连线圈以及具有将第二半导体管芯连接到第一隔离块的多条导线的第二互连线圈。

公开(公告)号：EP1494281A3

公开(公告)日：2009-03-11

申请号：EP03026554.0

申请日：2003-11-18

申请人： NORTHROP GRUMMAN CORPORATION

发明人： Hathaway, James A. ,  Crossman, Brian F. ,  Din, Salah

IPC分类号： H01L23/498 ,  H01L23/66

CPC分类号： H01L23/66 ,  H01L23/49816 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099

摘要： An electronic device packaging assembly (10) that includes a ball grid array (60) and specialized construction to be able to operate from DC up to 50 GHz with minimal parasitic losses. The packaging assembly (10) includes a thin base plate (14) made of a suitable rigid material. Power vias (48), signal vias (26) and ground vias (46) are formed through the base plate (14) to be coupled to traces, circuit components, and/or the device (12) within the packaging assembly (10). An impedance matching compensation network (28) provides impedance matching between the device (12) and the signal vias (26). The ball grid array (60) includes a plurality of solder balls (68), including ground solder balls (72), signal solder balls (74) and power solder balls (76), electrically coupled to the appropriate via extending through the base plate (14).