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    Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance
    2.
    发明公开
    Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance 有权
    一种用于识别具有差的或弱跨导非易失性存储元件的方法Subschwellensteigung

    公开(公告)号：EP2015310A3

    公开(公告)日：2009-04-15

    申请号：EP08004345.8

    申请日：2004-09-16

    申请人： SanDisk Corporation ,  Kabushiki Kaisha Toshiba

    发明人： Lutze, Jeffrey ,  Chen, Jian ,  Li, Yan ,  Kanebako, Kazunori ,  Tanaka, Tomoharu

    IPC分类号： G11C16/34 ,  G11C29/00

    CPC分类号： G11C16/3495 ,  G11C16/04 ,  G11C16/349 ,  G11C29/50 ,  G11C29/50004

    摘要： The present invention presents a number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behaviour of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behaviour by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.

    Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance
    3.
    发明公开
    Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance 有权
    一种用于识别具有差的或弱跨导非易失性存储元件的方法Subschwellensteigung

    公开(公告)号：EP2015310A2

    公开(公告)日：2009-01-14

    申请号：EP08004345.8

    申请日：2004-09-16

    申请人： SanDisk Corporation ,  Kabushiki Kaisha Toshiba

    发明人： Lutze, Jeffrey ,  Chen, Jian ,  Li, Yan ,  Kanebako, Kazunori ,  Tanaka, Tomoharu

    IPC分类号： G11C16/34 ,  G11C29/00

    CPC分类号： G11C16/3495 ,  G11C16/04 ,  G11C16/349 ,  G11C29/50 ,  G11C29/50004

    摘要： The present invention presents a number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behaviour of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behaviour by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.

    摘要翻译： 本发明提出用于识别与亚阈值斜率差和降低的互导单元的多种方法。 第一组的技术通过循环细胞，然后将它们编程到高于地面状态的状态和读取它们与该状态的阈值电压以下的控制栅极电压，以查看它们是否关闭退化的存储元件的差低于阈值的行为聚焦 开展。 第二组实施例中通过读取编程的单元的控制栅极电压远高于阈值电压上弱跨导行为对焦。 第三组实施例中在存储元件的源 - 漏区老化所述电压电平。 良好的存储元件的电流 - 电压曲线是这种转变在偏压条件下相对稳定，而退化的元件表现出更大的位移。 移位的量可被用于区分从好坏元件。

    Operating techniques for reducing the program and read disturbs of a non-volatile memory
    4.
    发明公开
    Operating techniques for reducing the program and read disturbs of a non-volatile memory 有权
    在非易失性存储器中减少编程和读取干扰技术

    公开(公告)号：EP1912223A1

    公开(公告)日：2008-04-16

    申请号：EP07011551.4

    申请日：2003-02-26

    申请人： SanDisk Corporation

    发明人： Li, Yan ,  Chen, Jian

    IPC分类号： G11C16/34 ,  G11C16/04

    CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/28 ,  G11C16/3418

    摘要： The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a Flash EEPROM memory with a NAND architecture that has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.

    摘要翻译： 本发明提出具有擦除单元或块，其中每个块被划分为部分共享相同的字线，以节省行译码器区域的多个A多个A的非易失性存储器，但是其可被读取或编程unabhängig。 有助于示例性实施例是具有NAND结构的快闪EEPROM存储器确实具有左和右一半，其中每个部分将容纳一个或多个标准页（数据传输单元）的512个字节的数据的大小构成的块。 在该示例性，实施例的左和右的块的每个部分具有单独的源极线和源极的独立套和漏极选择线。 在编程或左侧的读出，如实施例中，右侧可以被偏置以产生沟道升压以减少数据会干扰。 在一个备选组实施方案中，该部分可以有单独的阱结构。

    Non-volatile memory and method with power-saving read and program-verify operations
    6.
    发明公开
    Non-volatile memory and method with power-saving read and program-verify operations 审中-公开
    能源与电力公司（NichtflüchtigerSpeicher und Verfahren mit Energiesparlese- und-programmprüfvorgängen

    公开(公告)号：EP2169684A1

    公开(公告)日：2010-03-31

    申请号：EP10000203.9

    申请日：2005-05-10

    申请人： Sandisk Corporation

    发明人： Li, Yan ,  Lee, Seungpil ,  Chan, Siu Lung

    IPC分类号： G11C11/56

    CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C2211/5621

    摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by pre-emptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

    摘要翻译： 能够并行地读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有降低读取和编程/验证操作期间的功耗的特征。 读取或编程验证操作包括相对于一个或多个分界阈值电压的一个或多个感测周期，以确定存储器状态。 在一个方面，当被确定为处于与当前感测周期无关的状态时，被并联感测的组中的选择性存储单元的导通电流关闭。 另一方面，通过预先启动延长周期的任何操作来最大限度地减少功耗周期。 在程序/验证操作中，未编程的单元在程序阶段将其位线充电。 当一组这些位线避免在程序阶段的每次通过时重新充电，节省了电力。

    Non-volatile memory and its sensing method
    7.
    发明公开
    Non-volatile memory and its sensing method 有权
    非易失性存储器和读出过程

    公开(公告)号：EP1610335A3

    公开(公告)日：2008-08-06

    申请号：EP05077014.8

    申请日：2003-09-23

    申请人： SanDisk Corporation

    发明人： Cernea, Raul-Adrian ,  Li, Yan

    IPC分类号： G11C16/28 ,  G11C11/56 ,  G11C16/26 ,  G11C7/06

    CPC分类号： G11C7/06 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/28 ,  G11C29/02 ,  G11C29/026 ,  G11C2207/065

    摘要： A non-volatile memory has a plurality of sense amplifiers for sensing a group of memory storage units in parallel, each of said plurality of sense amplifiers having properties dependent on operating environment and a set of control signals. A reference circuit having elements with properties representative of a typical member of the sense amplifiers is located in a common operating environment with the sense amplifiers. In use, the set of control signals, responsive to said elements operating in the operating environment, is generated such that the sense amplifiers are controlled to have their properties substantially insensitive to the operating environment.

    Non-volatile memory and method for linear estimation of initial programming voltage
    10.
    发明公开
    Non-volatile memory and method for linear estimation of initial programming voltage 审中-公开
    非易失性存储器和方法，用于初始编程电压的线性估计

    公开(公告)号：EP2383748A2

    公开(公告)日：2011-11-02

    申请号：EP11175624.3

    申请日：2007-08-31

    申请人： SanDisk Corporation

    发明人： Tu, Loc ,  Hook, Charles Moana ,  Li, Yan

    IPC分类号： G11C16/12 ,  G11C16/04 ,  G11C29/02 ,  G11C29/50 ,  G11C16/34 ,  G11C11/56

    CPC分类号： G11C11/5628 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

    摘要： Non-Volatile Memory and Method for linear Estimation of Initial Programming Voltage
    In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.

    摘要翻译： 非易失性存储器和方法的初始编程电压的线性估计在非易失性存储器，对字线的选择的页连续地通过一系列在脉冲之间验证阶梯波形的电压脉冲的编程，直到该页 验证到指定模式。 在页面被编程验证时的编程电压将是估计开始编程电压为页面的初始值。 估计是进一步通过使用从估计在第二遍中的第一通细化。 这样，当测试是在多个块，基于块的相似几何位置字线采样可以产生起始编程电压更快的编程页面优化。