公开(公告)号：EP2132873A2

公开(公告)日：2009-12-16

申请号：EP08744804.9

申请日：2008-03-31

申请人： Sandisk 3D LLC

发明人： THORP, Tyler J. ,  FASOLI, Luca G.

IPC分类号： H03K19/0185

CPC分类号： H03K3/35613 ,  H03K17/102 ,  H03K19/01721

摘要： Level shift circuits are disclosed for level shifting an input signal corresponding to a first voltage domain, to generate a pair of complementary output signals corresponding to a second, higher-voltage domain. Snap-back sensitive devices in a discharge circuit for a high voltage output node are protected, irrespective of the loading on the output node, and without requiring precise transistor sizing as a function of the output loading. The snap-back sensitive devices are protected by a voltage shifter circuit in series with the sensitive devices, to limit the voltage across the sensitive devices, even for a high capacitance output node at its highest output voltage. The voltage shifter circuit is then bypassed to provide for an output low level that fully reaches the lower power supply rail.

公开(公告)号：EP2132873B1

公开(公告)日：2012-08-22

申请号：EP08744804.9

申请日：2008-03-31

申请人： Sandisk 3D LLC

发明人： THORP, Tyler J. ,  FASOLI, Luca G.

IPC分类号： H03K19/0185 ,  H03K17/10 ,  H03K19/017

CPC分类号： H03K3/35613 ,  H03K17/102 ,  H03K19/01721

摘要： Level shift circuits are disclosed for level shifting an input signal corresponding to a first voltage domain, to generate a pair of complementary output signals corresponding to a second, higher-voltage domain. Snap-back sensitive devices in a discharge circuit for a high voltage output node are protected, irrespective of the loading on the output node, and without requiring precise transistor sizing as a function of the output loading. The snap-back sensitive devices are protected by a voltage shifter circuit in series with the sensitive devices, to limit the voltage across the sensitive devices, even for a high capacitance output node at its highest output voltage. The voltage shifter circuit is then bypassed to provide for an output low level that fully reaches the lower power supply rail.

公开(公告)号：EP2052390B1

公开(公告)日：2015-06-03

申请号：EP07799950.6

申请日：2007-07-31

申请人： SanDisk 3D LLC

发明人： SCHEUERLEIN, Roy E. ,  THORP, Tyler J. ,  FASOLI, Luca G.

IPC分类号： G11C13/00 ,  G11C11/56 ,  G11C16/24 ,  G11C16/26

CPC分类号： G11C11/56 ,  G11C11/5642 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/24 ,  G11C16/26 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2211/5634 ,  G11C2213/77

公开(公告)号：EP2052390A2

公开(公告)日：2009-04-29

申请号：EP07799950.6

申请日：2007-07-31

申请人： Sandisk 3D LLC

发明人： SCHEUERLEIN, Roy E. ,  THORP, Tyler J. ,  FASOLI, Luca G.

IPC分类号： G11C16/04

CPC分类号： G11C11/56 ,  G11C11/5642 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/24 ,  G11C16/26 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2211/5634 ,  G11C2213/77

摘要： A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10. The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current is sensed for at least two different combinations of reference current level and read bias voltage. A mid-level reference is used to read the LSB. When reading the MSB, a first reference between the 10 and 00 data states, and a second reference between 01 and 11 data states may be used, and the mid-level reference need not be used. In certain embodiments, the bit line current may be simultaneously compared against the first and second references, without requiring a delay to stabilize the bit line current to a different value, and the MSB generated accordingly.