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16 条记录 (耗时 0.016 秒)

    REVERSIBLE POLARITY DECODER CIRCUIT AND RELATED METHODS
    4.
    发明公开
    REVERSIBLE POLARITY DECODER CIRCUIT AND RELATED METHODS 有权
    可逆极性和相关手续解码器电路

    公开(公告)号：EP2109863A1

    公开(公告)日：2009-10-21

    申请号：EP07869534.3

    申请日：2007-12-19

    申请人： Sandisk 3D LLC

    发明人： YAN, Tianhong ,  FASOLI, Luca G. ,  SCHEUERLEIN, Roy E.

    IPC分类号： G11C11/413

    CPC分类号： G11C8/08 ,  G11C13/00 ,  G11C13/0023 ,  G11C13/0028 ,  G11C2213/77

    摘要： A reversible polarity decoder circuit is disclosed which is particularly suitable for implementing a multi-headed decoder structure, such as might be used for decoding word lines, and particularly in a 3D memory array. The decoder circuit provides an overdrive voltage bias to the gates of half-selected word line driver circuits to solidly maintain the half-selected word lines at an inactive level. If the memory array is biased at or near the breakdown voltage, this overdrive voltage may be greater than the breakdown voltage of the decoder transistors. However, in the embodiments described, the decoder circuit accomplishes this without impressing a voltage greater than the breakdown voltage across any of the decoder transistors, for either polarity of operation of the decoder circuit.

    METHOD AND APPARATUS FOR READING A MULTI-LEVEL PASSIVE ELEMENT MEMORY CELL ARRAY
    5.
    发明公开
    METHOD AND APPARATUS FOR READING A MULTI-LEVEL PASSIVE ELEMENT MEMORY CELL ARRAY 有权
    方法和设备，用于读取多层次的无源元件的存储单元矩阵

    公开(公告)号：EP2052390A2

    公开(公告)日：2009-04-29

    申请号：EP07799950.6

    申请日：2007-07-31

    申请人： Sandisk 3D LLC

    发明人： SCHEUERLEIN, Roy E. ,  THORP, Tyler J. ,  FASOLI, Luca G.

    IPC分类号： G11C16/04

    CPC分类号： G11C11/56 ,  G11C11/5642 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/24 ,  G11C16/26 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2211/5634 ,  G11C2213/77

    摘要： A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10. The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current is sensed for at least two different combinations of reference current level and read bias voltage. A mid-level reference is used to read the LSB. When reading the MSB, a first reference between the 10 and 00 data states, and a second reference between 01 and 11 data states may be used, and the mid-level reference need not be used. In certain embodiments, the bit line current may be simultaneously compared against the first and second references, without requiring a delay to stabilize the bit line current to a different value, and the MSB generated accordingly.

    METHOD AND APPARATUS FOR DUAL DATA-DEPENDENT BUSSES FOR COUPLING READ/WRITE CIRCUITS TO A MEMORY ARRAY
    7.
    发明授权
    METHOD AND APPARATUS FOR DUAL DATA-DEPENDENT BUSSES FOR COUPLING READ/WRITE CIRCUITS TO A MEMORY ARRAY 有权
    方法和设备双数据驱动的总线系统，用于连接读取/写入电路到存储

    公开(公告)号：EP2062263B1

    公开(公告)日：2012-05-02

    申请号：EP07840621.2

    申请日：2007-07-31

    申请人： Sandisk 3D LLC

    发明人： SCHEUERLEIN, Roy E. ,  FASOLI, Luca G.

    IPC分类号： G11C11/00 ,  G11C8/00

    CPC分类号： G11C8/12 ,  G11C7/1048 ,  G11C7/18 ,  G11C8/08

    摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

    LEVEL SHIFTER CIRCUIT INCORPORATING TRANSISTOR SNAP-BACK PROTECTION
    9.
    发明公开
    LEVEL SHIFTER CIRCUIT INCORPORATING TRANSISTOR SNAP-BACK PROTECTION 有权
    由于晶体管EINSCHNAPPSCHUTZ电平变换电路

    公开(公告)号：EP2132873A2

    公开(公告)日：2009-12-16

    申请号：EP08744804.9

    申请日：2008-03-31

    申请人： Sandisk 3D LLC

    发明人： THORP, Tyler J. ,  FASOLI, Luca G.

    IPC分类号： H03K19/0185

    CPC分类号： H03K3/35613 ,  H03K17/102 ,  H03K19/01721

    摘要： Level shift circuits are disclosed for level shifting an input signal corresponding to a first voltage domain, to generate a pair of complementary output signals corresponding to a second, higher-voltage domain. Snap-back sensitive devices in a discharge circuit for a high voltage output node are protected, irrespective of the loading on the output node, and without requiring precise transistor sizing as a function of the output loading. The snap-back sensitive devices are protected by a voltage shifter circuit in series with the sensitive devices, to limit the voltage across the sensitive devices, even for a high capacitance output node at its highest output voltage. The voltage shifter circuit is then bypassed to provide for an output low level that fully reaches the lower power supply rail.