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    ION IMPLANTATION SYSTEM AND CONTROL METHOD
    3.
    发明公开
    ION IMPLANTATION SYSTEM AND CONTROL METHOD 审中-公开
    离子注入系统和控制程序

    公开(公告)号：EP1347804A1

    公开(公告)日：2003-10-01

    申请号：EP01944435.5

    申请日：2001-06-12

    申请人： Semequip, Inc.

    发明人： HORSKY, Thomas, N. ,  COHEN, Brian, C. ,  KRULL, Wade, A. ,  SACCO, George, P., Jr.

    IPC分类号： A61N5/00 ,  H01J7/24

    CPC分类号： H01J27/205 ,  H01J37/08 ,  H01J37/3171 ,  H01J2237/0473 ,  H01J2237/0475 ,  H01J2237/0812 ,  H01J2237/082

    摘要： Ion implantation with high brightness, ion beam by ionizing gas or vapor, e.g. of dimers, or decaborane, by direct electron impact ionization adjacent the outlet aperture (46, 176) of the ionization chamber (80; 175)). Preferably: conditions are maintained that produce a substantial ion density and limit the transverse kinetic energy of the ions to less than 0.7 eV; width of the ionization volume adjacent the aperture is limited to width less than about three times the width of the aperture; the aperture is extremely elongated; magnetic fields are avoided or limited; low ion beam noise is maintained; conditions within the ionization chamber are maintained that prevent formation of an arc discharge. With ion beam optics, such as the batch implanter of Figure (20), or in serial implanters, ions from the ion source are transported to a target surface and implanted; advantageously, in some cases, in conjunction with acceleration-deceleration beam lines employing cluster ion beams. Also disclosed are electron gun constructions, ribbon sources for electrons and ionization chamber configurations. Forming features of semiconductor devices, e.g. drain extensions of CMOS devices, and doping of flat panels are shown.

    A SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE
    5.
    发明公开
    A SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 审中-公开
    半导体器件和制造半导体器件的方法

    公开(公告)号：EP1540720A2

    公开(公告)日：2005-06-15

    申请号：EP03761936.8

    申请日：2003-06-18

    申请人： Semequip, Inc.

    发明人： KRULL, Wade, A. ,  JACOBSON, Dale, C.

    IPC分类号： H01L21/425

    CPC分类号： H01L21/2255 ,  H01L21/265 ,  H01L21/28035 ,  H01L21/28105 ,  H01L21/28114 ,  H01L21/32155 ,  H01L29/1045 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

    摘要： A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation. The second deposition, with an associated ion implant for doping, completes the gate electrode. With the two-deposition process, it is possible to maximize the doping at the gate electrode/gate dielectric interface while minimizing risk of boron penetration of the gate dielectric. A further development of this method includes the patterning of both gate electrode layers with the advantage of utilizing the drain extension and source/drain implants as the gate doping implants and the option of offsetting the two patterns to create an asymmetric device. A method is also provided for the formation of shallow junctions in a semiconductor substrate by diffusion of dopant from an implanted layer contained within a dielectric layer into the semiconductor surface. Further, the ion implanted layer is provided with a second implanted species, such as hydrogen, in addition to the intended dopant species, wherein said species enhances the diffusivity of the dopant in the dielectric layer.

    摘要翻译： 提出了一种用于制造半导体器件的栅极的方法，使得栅极耗尽的影响最小化。 该方法包括双沉积工艺，其中第一步是非常薄的层，其通过离子注入非常严重地掺杂。 第二次沉积（用于掺杂的相关离子注入）完成了栅电极。 利用双沉积工艺，可以最大化栅电极/栅极介电界面处的掺杂，同时最小化硼渗透栅极电介质的风险。 该方法的进一步发展包括利用漏极扩展和源极/漏极注入作为栅极掺杂注入以及偏移这两个图案以创建不对称器件的优点，对两个栅极电极层进行构图。 还提供了一种方法，用于通过将掺杂剂从包含在介电层内的注入层扩散到半导体表面中来在半导体衬底中形成浅结。 此外，除了预期的掺杂剂物质之外，离子注入层还提供有第二注入物质，例如氢，其中所述物质增强了介质层中掺杂剂的扩散性。