公开(公告)号：EP2259292B1

公开(公告)日：2017-10-25

申请号：EP10178860.2

申请日：1999-11-16

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Yamazaki, Shunpei

IPC分类号： H01L51/52 ,  H01L21/336 ,  H01L21/84 ,  H01L21/28 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L27/12 ,  H01L27/32

CPC分类号： H01L27/3262 ,  H01L21/28114 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/3244 ,  H01L27/3248 ,  H01L29/42384 ,  H01L29/66492 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78675 ,  H01L29/78696 ,  H01L51/5256 ,  H01L2029/7863 ,  H01L2227/32

公开(公告)号：EP3084836A4

公开(公告)日：2017-07-12

申请号：EP14872869

申请日：2014-12-02

申请人： INTEL CORP

发明人： STEIGERWALD JOSEPH M ,  GHANI TAHIR ,  HU JENNY ,  POST IAN R C

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/7831 ,  H01L21/28114 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4908 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78645

摘要： Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了多阈值电压器件以及相关联的技术和配置。 在一个实施例中，一种装置包括半导体衬底，布置在半导体衬底上的沟道主体，具有与沟道主体耦合的第一厚度的第一栅电极和具有与沟道主体耦合的第二厚度的第二栅电极，其中， 第一厚度大于第二厚度。 其他实施例可以被描述和/或要求保护。

公开(公告)号：EP3084836A1

公开(公告)日：2016-10-26

申请号：EP14872869.4

申请日：2014-12-02

申请人： Intel Corporation

发明人： STEIGERWALD, Joseph M. ,  GHANI, Tahir ,  HU, Jenny ,  POST, Ian R.C.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7831 ,  H01L21/28114 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4908 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78645

摘要： Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了多阈值电压器件和相关的技术和配置。 在一个，装置的实施方式包括半导体基板，沟道体设置在所述半导体衬底，其具有耦合与通道体和具有耦合与通道本体的第二厚度的第二栅电极的第一厚度的第一栅电极，worin的 第一厚度比所述第二厚度大。 其它实施例可以被描述和/或要求保护。

公开(公告)号：EP1868247B1

公开(公告)日：2013-04-24

申请号：EP06425396.6

申请日：2006-06-13

申请人： STMicroelectronics Srl

发明人： Cascino, Salvatore ,  Nicotra, Maria Concetta ,  Santangelo, Antonello

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/423 ,  H01L21/28 ,  H01L29/10

CPC分类号： H01L29/42376 ,  H01L21/28114 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/66484 ,  H01L29/66659 ,  H01L29/7831 ,  H01L29/7835

公开(公告)号：EP1535344B1

公开(公告)日：2012-11-21

申请号：EP03788285.9

申请日：2003-07-28

申请人： Semiconductor Components Industries, LLC

发明人： GRIVNA, Gordon, M.

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/28114 ,  H01L21/2815 ,  H01L29/42304 ,  H01L29/42376 ,  H01L29/66272 ,  H01L29/66712 ,  H01L29/7322 ,  H01L29/7811

摘要： A transistor ( 10 ) is formed in a semiconductor substrate ( 12 ) whose top surface ( 48 ) is formed with a pedestal structure ( 24 ). A conductive material ( 40 ) is disposed along a side surface ( 28 ) of the pedestal structure to self-align an edge of a first conduction electrode ( 45 ) of the transistor. A dielectric spacer ( 55 ) is formed along a side surface ( 49 ) of the conductive material to self-align a contact area ( 56 ) of the first conduction electrode.

公开(公告)号：EP1952433B1

公开(公告)日：2012-07-25

申请号：EP06829916.3

申请日：2006-10-19

申请人： International Business Machines Corporation

发明人： HORAK, David, Vaclav ,  HAKEY, Mark, Charles ,  HOLMES, Steven, John ,  FURUKAWA, Toshiharu ,  KOBURGER, Charles, William, III ,  TONTI, William, Robert

IPC分类号： H01L21/28 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28114

摘要： A structure and a method for forming the same. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically insulated from the channel region by the gate dielectric region; (d) a protection umbrella region on the gate region, wherein the protection umbrella region comprises a first dielectric material, and wherein the gate region is completely in a shadow of the protection umbrella region; and (e) a filled contact hole (i) directly above and electrically connected to the second S/D region and (ii) aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by an inter-level dielectric (ILD) layer which comprises a second dielectric material different from the first dielectric material.

公开(公告)号：EP1469525B1

公开(公告)日：2011-05-25

申请号：EP03258260.3

申请日：2003-12-31

申请人： Electronics and Telecommunications Research Institute

发明人： Cheong, Woo Seok, c/o 136-305 Hanbit Apt. ,  Jang, Moon Gyu, c/o Rm. 302 Chowon Villa ,  Lee, Seong Jae, c/o 106-1106 Daerim Apt.

IPC分类号： H01L29/78 ,  H01L29/786 ,  H01L29/08 ,  H01L21/336

CPC分类号： H01L21/28114 ,  H01L21/28123 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/7839 ,  H01L29/78654

公开(公告)号：EP1435107B1

公开(公告)日：2010-03-31

申请号：EP02790287.3

申请日：2002-10-02

申请人： Infineon Technologies AG

发明人： HERZUM, Christian ,  MÜLLER, Karlheinz

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L21/28202 ,  H01L21/28114 ,  H01L21/2815 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/518

公开(公告)号：EP1728274A2

公开(公告)日：2006-12-06

申请号：EP05711888.7

申请日：2005-01-21

申请人： Freescale Semiconductor, Inc.

发明人： ORLOWSKI, Marius K. ,  BURNETT, James D.

IPC分类号： H01L21/4763 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/28114

摘要： A method for forming a semiconductor device (10) includes providing a substrate (20) having a surface; forming an insulating layer (22) over the surface of the substrate (20); forming a first patterned conductive layer (30) over the insulating layer (22); forming a second patterned conductive layer (32) over the first patterned conductive layer (30); forming a patterned non-insulating layer (34) over the second patterned conductive layer (32); and selectively removing portions of the first and second patterned conductive layers (30, 32) to form a notched control electrode for the semiconductor device (10).

公开(公告)号：EP1540720A2

公开(公告)日：2005-06-15

申请号：EP03761936.8

申请日：2003-06-18

申请人： Semequip, Inc.

发明人： KRULL, Wade, A. ,  JACOBSON, Dale, C.

IPC分类号： H01L21/425

CPC分类号： H01L21/2255 ,  H01L21/265 ,  H01L21/28035 ,  H01L21/28105 ,  H01L21/28114 ,  H01L21/32155 ,  H01L29/1045 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

摘要： A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation. The second deposition, with an associated ion implant for doping, completes the gate electrode. With the two-deposition process, it is possible to maximize the doping at the gate electrode/gate dielectric interface while minimizing risk of boron penetration of the gate dielectric. A further development of this method includes the patterning of both gate electrode layers with the advantage of utilizing the drain extension and source/drain implants as the gate doping implants and the option of offsetting the two patterns to create an asymmetric device. A method is also provided for the formation of shallow junctions in a semiconductor substrate by diffusion of dopant from an implanted layer contained within a dielectric layer into the semiconductor surface. Further, the ion implanted layer is provided with a second implanted species, such as hydrogen, in addition to the intended dopant species, wherein said species enhances the diffusivity of the dopant in the dielectric layer.

摘要翻译： 提出了一种用于制造半导体器件的栅极的方法，使得栅极耗尽的影响最小化。 该方法包括双沉积工艺，其中第一步是非常薄的层，其通过离子注入非常严重地掺杂。 第二次沉积（用于掺杂的相关离子注入）完成了栅电极。 利用双沉积工艺，可以最大化栅电极/栅极介电界面处的掺杂，同时最小化硼渗透栅极电介质的风险。 该方法的进一步发展包括利用漏极扩展和源极/漏极注入作为栅极掺杂注入以及偏移这两个图案以创建不对称器件的优点，对两个栅极电极层进行构图。 还提供了一种方法，用于通过将掺杂剂从包含在介电层内的注入层扩散到半导体表面中来在半导体衬底中形成浅结。 此外，除了预期的掺杂剂物质之外，离子注入层还提供有第二注入物质，例如氢，其中所述物质增强了介质层中掺杂剂的扩散性。