公开(公告)号：EP1246258B1

公开(公告)日：2011-02-23

申请号：EP00986014.9

申请日：2000-12-28

申请人： Sharp Kabushiki Kaisha

发明人： IWATA, Hiroshi ,  SHIBATA, Akihide ,  KAKIMOTO, Seizo ,  ADACHI, Kouichiro ,  NAKANO, Masayuki LM Narayasuraginomichi 201

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/225

CPC分类号： H01L29/66628 ,  H01L21/2251 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/78657

摘要： A semiconductor device (1910) comprises a semiconductor substrate (100) including an isolation region (101) and an active region (102); a gate electrode (104) formed on gate oxide film (103) over the active area (102) and including side walls covered at least in part by insulating film (105) of the gate electrode side wall; and a source region (106) and a drain region (106) provided across the gate electrode (104) with the insulating film (105) of the gate electrode side wall in between. At least any of the source region (106) and the drain region (106) includes a second face for engagement with contact wiring. The second face makes some angle with the first face (AA') and an angle of less than 80 degrees with the surface of the isolation region.

公开(公告)号：EP1343207B1

公开(公告)日：2009-10-07

申请号：EP01982765.8

申请日：2001-11-13

申请人： Sharp Kabushiki Kaisha

发明人： SHIBATA, Akihide ,  IWATA, Hiroshi ,  KAKIMOTO, Seizo

IPC分类号： H01L27/092

CPC分类号： H01L21/76229 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0921

摘要： A semiconductor device of low power consumption and high reliability with a DTMOS and a substrate bias variable transistor and a portable electronic apparatus comprising this semiconductor device. This device has three layer well regions (12, 14, 16; 13, 15, 16) on a semiconductor substrate (11) and is provided with DTMOSs (29, 30), and substrate bias variable transistors (27, 28) in shallow well regions (16, 17). A boundary which constitutes a PNP, an NPN, or an NPNP structure is provided with wide element isolating regions (181, 182, 183), but a narrow element isolating region (18) when both the well regions have the same conductivity type. Thus, a plurality of well regions of respective conductivity types provided with substrate bias variable transistors (27, 28) of the respective conductivity types are made electrically independent to reduce power consumption and to suppress latchup phenomenon.

公开(公告)号：EP1100128B1

公开(公告)日：2009-04-15

申请号：EP99926834.5

申请日：1999-06-29

申请人： Sharp Kabushiki Kaisha

发明人： IWATA, Hiroshi ,  KAKIMOTO, Seizo ,  NAKANO, Masayuki LM Nara Yasuraginomichi 201 ,  ADACHI, Kouichiro

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/783 ,  H01L21/84 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78615 ,  H01L29/78618 ,  H01L29/78654

摘要： A semiconductor device comprises a semiconductor substrate, isolation regions formed in the semiconductor substrate, a semiconductor layer of a first conductivity type formed between the isolation regions, a gate oxide layer formed on an active region of the semiconductor layer of the first conductivity type, a gate electrode formed on the gate oxide layer, an insulating layer formed on the sidewall of the gate electrode, and a semiconductor layer of a second conductivity type for source/drain formed adjacent to the insulating layer on the sidewall of the gate electrode and intended to cover part of the isolation regions. The gate electrode and the semiconductor layer of the first conductivity type are connected electrically, the semiconductor layer of the second conductivity type is formed above the semiconductor layer of the first conductivity type, and the thickness of the semiconductor layer of the second conductivity type is such that it gradually increases as the layer extends from the isolation region toward the gate electrode.

公开(公告)号：EP1335425A1

公开(公告)日：2003-08-13

申请号：EP01976761.5

申请日：2001-10-19

申请人： Sharp Kabushiki Kaisha

发明人： IWATA, Hiroshi ,  SHIBATA, Akihide ,  KAKIMOTO, Seizo

IPC分类号： H01L21/8234 ,  H01L27/08 ,  H01L29/78 ,  H01L21/336 ,  H01L21/76 ,  H01L21/761

CPC分类号： H01L21/823481 ,  H01L21/761 ,  H01L21/76202 ,  H01L21/76232 ,  H01L21/823493

摘要： A semiconductor device having a two-layer well structure and a small margin required at the boundary of a well region and comprising a substrate-bias variable transistor and a DTMOS. Field effect transistors (223) are formed on a P-type shallow well region (212). The depth of a shallow device isolation region (214) on the P-type shallow well region (212) is less than the depth of the junction between an N-type deep well region (227) and the P-type shallow well region (212). Therefore the field effect transistors (223) share the P-type shallow well region (212). The P-type shallow well regions (212) independently of each other are easily formed since they are isolated from each other by a deep device isolation region (226) and the N-type deep well region (227).

摘要翻译： 一种半导体器件，其具有在阱区的边界处所需的两层阱结构和小的边界，并且包括衬底偏置可变晶体管和DTMOS。 场效应晶体管（223）形成在P型浅阱区（212）上。 P型浅井区域（212）上的浅装置隔离区域（214）的深度小于N型深井区域（227）和P型浅井区域（ 212）。 因此，场效应晶体管（223）共享P型浅阱区（212）。 彼此独立的P型浅阱区域（212）由于它们通过深度器件隔离区域（226）和N型深阱区域（227）彼此隔离而容易地形成。

公开(公告)号：EP1357598A1

公开(公告)日：2003-10-29

申请号：EP01271852.4

申请日：2001-12-21

申请人： Sharp Kabushiki Kaisha

发明人： SHIBATA, Akihide ,  IWATA, Hiroshi ,  KAKIMOTO, Seizo

IPC分类号： H01L27/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/76 ,  H01L21/761

CPC分类号： H01L27/0928 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892

摘要： There is provided a semiconductor device including DTMOS and a substrate variable-bias transistor and a portable electronic device both operable with reduced power consumption. N-type deep well regions (12) are formed in one P-type semiconductor substrate (11). The N-type deep well regions (12, 12) are electrically isolated by the P-type semiconductor substrate (11). Over the N-type deep well regions (12), a P-type deep well region (13) and a P-type shallow well region (15) are formed to fabricate an N-type substrate variable-bias transistor (26). Over the N-type deep well region (12), an N-type shallow well region (14) is formed to fabricate a P-type substrate variable-bias transistor (25). Further a P-type DTMOS (28) and an N-type DTMOD (27) are fabricated.

摘要翻译： 提供了包括DTMOS和基板可变偏置晶体管的半导体器件以及可以以降低的功耗进行操作的便携式电子设备。 在一个P型半导体衬底（11）中形成N型深阱区（12）。 N型深阱区域（12,12）由P型半导体衬底（11）电隔离。 在N型深阱区域（12）上形成有P型深阱区域（13）和P型浅阱区域（15），以制造N型衬底可变偏压晶体管（26）。 在N型深井区域（12）上形成有N型浅井区域（14），以制造P型衬底可变偏压晶体管（25）。 此外，还制作了P型DTMOS（28）和N型DTMOD（27）。

公开(公告)号：EP1343207A1

公开(公告)日：2003-09-10

申请号：EP01982765.8

申请日：2001-11-13

申请人： Sharp Kabushiki Kaisha

发明人： SHIBATA, Akihide ,  IWATA, Hiroshi ,  KAKIMOTO, Seizo

IPC分类号： H01L27/08 ,  H01L27/085 ,  H01L27/092 ,  G06F17/60

CPC分类号： H01L21/76229 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0921

摘要： There is provided a semiconductor device of low power consumption and high reliability having DTMOS' and substrate-bias variable transistors, and portable electronic equipment using the semiconductor device. On a semiconductor substrate (11), trilayer well regions (12, 14, 16; 13, 15, 16) are formed, and DTMOS' (29, 30) and substrate-bias variable transistors (27, 28) are provided in the shallow well regions (16, 17). Large-width device isolation regions (181, 182, 183) are provided at boundaries forming PNP, NPN or NPNP structures, where a small-width device isolation region (18) is provided on condition that well regions on both sides are of an identical conductive type. Thus, a plurality of well regions of individual conductive types where substrate-bias variable transistors (27, 28) of individual conductive types are provided can be made electrically independent of one another, allowing the power consumption to be reduced. Besides, the latch-up phenomenon can be suppressed.

摘要翻译： 提供了具有DTMOS和衬底偏置可变晶体管的低功耗和高可靠性的半导体器件，以及使用该半导体器件的便携式电子设备。 在半导体衬底（11）上，形成三层阱区域（12,14,16,13,15,16），并且在所述半导体衬底（11）上设置DTMOS（29,30）和衬底偏置可变晶体管（27,28） 浅井区（16,17）。 在形成PNP，NPN或NPNP结构的边界处提供大宽度器件隔离区（181,182,183），其中在两侧的阱区具有相同的条件下提供小宽度器件隔离区（18） 导电型。 因此，可以使提供单独导电类型的衬底偏置可变晶体管（27,28）的各种导电类型的多个阱区彼此电独立，从而降低功耗。 此外，可以抑制闩锁现象。

公开(公告)号：EP1246258A1

公开(公告)日：2002-10-02

申请号：EP00986014.9

申请日：2000-12-28

申请人： Sharp Kabushiki Kaisha

发明人： IWATA, Hiroshi ,  SHIBATA, Akihide ,  KAKIMOTO, Seizo ,  ADACHI, Kouichiro ,  NAKANO, Masayuki LM Narayasuraginomichi 201

IPC分类号： H01L29/78

CPC分类号： H01L29/66628 ,  H01L21/2251 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/78657

摘要： A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103 , part of a side of the gate electrode 104 being covered with a gate electrode side wall insulating film 105 , and a source region 106 and a drain region 106 provided on opposite sides of the gate electrode 104 via the gate electrode side wall insulating film 105 . At least one of the source region 106 and the drain region 106 has a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A-A' . An angle between the second surface and a surface of the isolation region is 80 degrees or less.

摘要翻译： 半导体器件1910包括半导体衬底100，其包括隔离区域101和有源区域102，经由栅极绝缘膜103设置在有源区域102上的栅电极104，栅电极104的一侧的一部分被覆盖有 栅电极侧壁绝缘膜105，以及经由栅电极侧壁绝缘膜105设置在栅极电极104的相对侧上的源极区域106和漏极区域106.源极区域106和漏极区域106中的至少一个 具有用于接触接触导体的第二表面。 第二表面相对于第一表面A-A'倾斜。 第二表面与隔离区域的表面之间的角度为80度以下。

公开(公告)号：EP1100128A1

公开(公告)日：2001-05-16

申请号：EP99926834.5

申请日：1999-06-29

申请人： Sharp Kabushiki Kaisha

发明人： IWATA, Hiroshi ,  KAKIMOTO, Seizo ,  NAKANO, Masayuki LM Nara Yasuraginomichi 201 ,  ADACHI, Kouichiro

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/783 ,  H01L21/84 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78615 ,  H01L29/78618 ,  H01L29/78654

摘要： A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other. The second conductivity type semiconductor layers are provided above the first conductivity type semiconductor layer and have a thickness which gradually increases from the device isolation region toward the gate electrode.

摘要翻译： 根据本发明的半导体器件包括半导体衬底; 设置在半导体衬底中的器件隔离区; 设置在所述器件隔离区之间的第一导电型半导体层; 设置在所述第一导电型半导体层的有源区上的栅极绝缘层; 设置在所述栅极绝缘层上的栅电极; 设置在栅极侧壁上的栅电极侧壁绝缘层; 以及与栅电极侧壁绝缘层相邻设置以覆盖相应器件隔离区的一部分的第二导电类型半导体层，第二导电类型半导体层用作源区和/或漏区。 栅电极和第一导电型半导体层彼此电连接。 第二导电类型半导体层设置在第一导电类型半导体层之上，并且具有从器件隔离区朝向栅极电极逐渐增加的厚度。