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    ARRANGEMENT AND METHOD FOR FACILITATING ELECTRONICS DESIGN IN CONNECTION WITH 3D STRUCTURES
    1.
    发明公开
    ARRANGEMENT AND METHOD FOR FACILITATING ELECTRONICS DESIGN IN CONNECTION WITH 3D STRUCTURES 审中-公开

    公开(公告)号：EP3514708A3

    公开(公告)日：2019-10-02

    申请号：EP18212427.1

    申请日：2018-12-13

    申请人： TactoTek Oy

    发明人： SINIVAARA, Hasse ,  HEIKKILÄ, Tuomas ,  KERÄNEN, Antti

    IPC分类号： G06F17/50

    摘要： An electronic arrangement for facilitating circuit layout design in connection with three-dimensional (3D) target designs, the arrangement including at least one communication interface for transferring data, at least one processor for processing instructions and other data, and a memory for storing the instructions and other data. The at least one processor being configured, in accordance with the stored instructions, to cause: obtaining and storing information in a data repository hosted by the memory, receiving design input characterizing 3D target design to be produced from a substrate, determining a mapping between locations of the 3D target design and the substrate, and establishing and providing digital output comprising human and/or machine readable instructions indicative of the mapping to a receiving entity, such as a manufacturing equipment, e.g. printing, electronics assembly and/or forming equipment.

    METHOD FOR MANUFACTURING A STRAIN GAUGE DEVICE, A STRAIN GAUGE DEVICE AND THE USE OF THE DEVICE
    2.
    发明公开
    METHOD FOR MANUFACTURING A STRAIN GAUGE DEVICE, A STRAIN GAUGE DEVICE AND THE USE OF THE DEVICE 审中-公开

    公开(公告)号：EP3511146A2

    公开(公告)日：2019-07-17

    申请号：EP18214591.2

    申请日：2018-12-20

    申请人： TactoTek Oy

    发明人： KERÄNEN, Antti ,  HEIKKINEN, Mikko ,  BRÄYSY, Vinski

    IPC分类号： B29C45/14 ,  B29C45/16 ,  G01L1/14

    摘要： A method for manufacturing a strain gauge device and a strain gauge device (20) are presented. The method comprises obtaining (11) a first substrate (21A), preferably a first formable substrate film (21A) for accommodating electronic components, printing (12) by a printed electronics method, such as by screen printing or inkjet printing, a strain gauge (22) on the first substrate (21A), and molding (14), preferably by utilizing injection molding, a molded material layer (23) embedding the strain gauge (22). The strain gauge device (20) may comprise two, preferably formable, substrate films between which the strain gauge (22) and the molded material layer (23) may be arranged.

    ARRANGEMENT AND METHOD FOR FACILITATING ELECTRONICS DESIGN IN CONNECTION WITH 3D STRUCTURES
    3.
    发明公开
    ARRANGEMENT AND METHOD FOR FACILITATING ELECTRONICS DESIGN IN CONNECTION WITH 3D STRUCTURES 审中-公开

    公开(公告)号：EP3499393A1

    公开(公告)日：2019-06-19

    申请号：EP18212430.5

    申请日：2018-12-13

    申请人： TactoTek Oy

    发明人： SINIVAARA, Hasse ,  HEIKKILÄ, Tuomas ,  KERÄNEN, Antti

    IPC分类号： G06F17/50

    摘要： An electronic arrangement for facilitating circuit layout design in connection with three-dimensional (3D) target designs, the arrangement including at least one communication interface for transferring data, at least one processor for processing instructions and other data, and a memory for storing the instructions and other data. The at least one processor being configured, in accordance with the stored instructions, to cause: obtaining and storing information in a data repository hosted by the memory, receiving design input characterizing 3D target design to be produced from a substrate, determining a mapping between locations of the 3D target design and the substrate, and establishing and providing digital output comprising human and/or machine readable instructions indicative of the mapping to a receiving entity, such as a manufacturing equipment, e.g. printing, electronics assembly and/or forming equipment.

    MULTILAYER STRUCTURE WITH EMBEDDED LIGHT SOURCE AND LIGHT-GUIDING FEATURES AND RELATED METHOD OF MANUFACTURE
    4.
    发明公开
    MULTILAYER STRUCTURE WITH EMBEDDED LIGHT SOURCE AND LIGHT-GUIDING FEATURES AND RELATED METHOD OF MANUFACTURE 审中-公开

    公开(公告)号：EP4283351A2

    公开(公告)日：2023-11-29

    申请号：EP23202905.8

    申请日：2019-12-05

    申请人： TactoTek Oy

    发明人： KERÄNEN, Antti ,  HEIKKINEN, Mikko

    IPC分类号： G02B6/00

    摘要： Integrated multilayer structure (100, 200, 300, 400, 600, 700), comprising a substrate film (102) having a first side and an opposing second side; electronics comprising at least one light source (110), optionally a LED, provided upon the first side of the substrate film and a number of electrical conductors (112), preferably printed by printed electronics technology, at least electrically coupled to the at least one light source (110), the at least one light source (110) being configured to emit light in selected one or more frequencies or wavelengths, optionally including visible light; an optically transmissive element (104) comprising thermoplastic optically transmissive, having regard to the selected frequencies or wavelengths, material having a first refractive index and produced, preferably through utilization of molding from said optically transmissive thermoplastic material, onto the first side of the substrate film (102) so as to at least partially embed the at least one light source (110) therewithin; and optical cladding (106, 106a, 106b) comprising material having a lower refractive index than the first refractive index and provided adjacent the optically transmissive element upon the first side of the substrate film (102), wherein the at least one light source, the optically transmissive element and the optical cladding have been mutually configured (702, 704) so as to convey light emitted by the light source (110) within the optically transmissive material of the optically transmissive element, at least portion of the conveyed light undergoing a substantially total internal reflection when incident upon the optical cladding. Related method of manufacture is presented.

    ARRANGEMENT AND METHOD FOR FACILITATING ELECTRONICS DESIGN IN CONNECTION WITH 3D STRUCTURES
    10.
    发明公开
    ARRANGEMENT AND METHOD FOR FACILITATING ELECTRONICS DESIGN IN CONNECTION WITH 3D STRUCTURES 审中-公开

    公开(公告)号：EP3514708A2

    公开(公告)日：2019-07-24

    申请号：EP18212427.1

    申请日：2018-12-13

    申请人： TactoTek Oy

    发明人： SINIVAARA, Hasse ,  HEIKKILÄ, Tuomas ,  KERÄNEN, Antti

    IPC分类号： G06F17/50

    摘要： An electronic arrangement for facilitating circuit layout design in connection with three-dimensional (3D) target designs, the arrangement including at least one communication interface for transferring data, at least one processor for processing instructions and other data, and a memory for storing the instructions and other data. The at least one processor being configured, in accordance with the stored instructions, to cause: obtaining and storing information in a data repository hosted by the memory, receiving design input characterizing 3D target design to be produced from a substrate, determining a mapping between locations of the 3D target design and the substrate, and establishing and providing digital output comprising human and/or machine readable instructions indicative of the mapping to a receiving entity, such as a manufacturing equipment, e.g. printing, electronics assembly and/or forming equipment.