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公开(公告)号：EP4064137A1
公开(公告)日：2022-09-28
申请号：EP21844599.7
申请日：2021-09-08
发明人： ZHOU, Yu , ZHANG, Zhenxing , AN, Shuoming , YIN, Zelong , HUAI, Sainan , GU, Xiu , XU, Xiong , ZHANG, Shengyu
IPC分类号： G06N10/00
摘要： The present disclosure discloses a quantum circuit and a quantum processor, relating to the field of quantum technologies. The quantum circuit includes: a qubit, a resonant cavity, and a feeder, the resonant cavity being coupled to the qubit, and the feeder being coupled to the qubit. The feeder is configured to feed an initialization signal to the qubit, the initialization signal being a modulation signal used for causing a frequency of the qubit to generate an oscillation. The oscillation causes an equivalent state exchange to occur between the qubit and the resonant cavity, and an excited state of the qubit is initialized to a ground state by using the resonant cavity. The present disclosure provides an efficient and high-precision qubit initialization solution. A modulation signal is applied to a qubit as an initialization signal, so that an excited state of the qubit quickly decays to a ground state by using a resonant cavity, thereby implementing rapid and high-fidelity initialization. In addition, a feedback loop does not need to be introduced to measure and read a state of the qubit, thereby reducing requirements for hardware.
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公开(公告)号：EP4398011A1
公开(公告)日：2024-07-10
申请号：EP23825938.6
申请日：2023-04-25
发明人： LI, Dengfeng , ZHANG, Wenlong , DAI, Maochun , BU, Kunliang , HUAI, Sainan
摘要： Provided in the present application are a method and apparatus for preparing a quantum chip, and an electronic device, a computer-readable storage medium, a computer program product and a quantum chip. The method comprises: determining an initial intrinsic frequency of a chip substrate; on the basis of a comparison result between the value of the initial intrinsic frequency and the value of a quantum working frequency, performing pattern etching treatment on a first surface of the chip substrate, so as to obtain a chip substrate which has a complete second surface and has a target pattern on the first surface, wherein the quantum working frequency is the working frequency of quantum bits of a quantum circuit, the second surface is opposite the first surface, and the target pattern is a pattern when the difference value between the intrinsic frequency of the chip substrate and the quantum working frequency is the maximum; and etching the second surface of the chip substrate which has been subjected to the pattern etching treatment,, so as to form the quantum circuit, thereby forming a quantum chip.
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公开(公告)号：EP4394647A1
公开(公告)日：2024-07-03
申请号：EP23866627.5
申请日：2023-05-18
发明人： LI, Yanghepu , MA, Shengming , WANG, Jianming , HUAI, Sainan , ZHANG, Shengyu , HUANG, Zhao , XU, Xiong
IPC分类号： G06F30/39
CPC分类号： G06F30/39 , G06F30/392 , G06F30/394
摘要： This application provides an airbridge arrangement method and apparatus for a chip layout, a device, and a storage medium, and in particular, relates to the field of chip technologies. The method includes: obtaining a coplanar waveguide (CPW) point set in the chip layout, where the CPW point set includes location information of n points for defining a CPW arranged in the chip layout, and n is an integer greater than 1 (210); determining a skeleton line of the CPW according to the location information of the n points in the CPW point set, where the skeleton line of the CPW is a center line of a center conductor of the CPW (220); and arranging airbridges on the chip layout according to the skeleton line of the CPW (230). In this application, the skeleton line of the CPW is automatically recognized and the airbridges are automatically arranged, thereby improving the universality of the airbridge arrangement method for a chip layout.
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4.发明公开
公开(公告)号：EP4390749A1
公开(公告)日：2024-06-26
申请号：EP23864158.3
申请日：2023-05-23
发明人： MA, Shengming , HU, An , ZHANG, Tianyu , HUAI, Sainan , ZHANG, Shengyu , HUANG, Zhao , XU, Xiong , LI, Yanghepu
IPC分类号： G06F30/392
摘要： An air bridge deployment method and apparatus in a circuit layout, a device, a medium, and a product are provided, and in particular, relate to the field of chip technologies. The method includes: obtaining position information of skeleton lines of CPW lines based on position information of the CPW lines in the circuit layout, each skeleton line being a center line of a respective CPW line (320); obtaining an interweave pair from the skeleton lines of the CPW lines based on the position information of the skeleton lines of the CPW lines, the interweave pair including two interweaved skeleton lines (330); and deploying air bridges on the circuit layout along the skeleton lines, and the air bridges on the two skeleton lines in the interweave pair being arranged in a staggered manner (340). According to the foregoing solution, impacts between air bridges on different CPW lines are reduced, and a success rate of subsequent circuit fabrication is improved.
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公开(公告)号：EP4400999A1
公开(公告)日：2024-07-17
申请号：EP23869660.3
申请日：2023-05-23
发明人： MA, Shengming , CHEN, Yue , WANG, Jianming , HUAI, Sainan , ZHANG, Shengyu , XU, Xiong
IPC分类号： G06F30/394
CPC分类号： G06F30/394
摘要： The present disclosure discloses a circuit layout routing method and apparatus, a device, a storage medium, and a product, and relates to the field of micro-nano processing technologies. The method includes: obtaining position information of at least one routing point in a circuit layout from routing planning information of the circuit layout (41); calculating, based on the position information, a turning starting position and a turning radius corresponding to each of the at least one routing point (42); and generating a routing path through the at least one routing point based on the turning starting position and the turning radius, the routing path turning at the turning starting position with the turning radius (43). The foregoing solution expands an applicable scenario of an automatic routing algorithm.
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公开(公告)号：EP4053923A1
公开(公告)日：2022-09-07
申请号：EP21854663.8
申请日：2021-09-08
发明人： ZHOU, Yu , ZHANG, Zhenxing , HUAI, Sainan , ZHENG, Yarui , ZHANG, Shengyu
摘要： This disclosure provides a superconducting quantum hybrid system, a computer device, and a quantum chip, and relates to the field of quantum computing. The superconducting quantum hybrid system includes: a silicon carbide (SiC) epitaxial layer and a superconducting qubit line, where the superconducting qubit line corresponds to a superconducting qubit; a designated region of the SiC epitaxial layer includes a nitrogen vacancy (NV) center, the NV center being formed by implanting nitrogen ions into the SiC epitaxial layer in the designated region; the superconducting qubit line is located on a surface of the SiC epitaxial layer; and the superconducting qubit line is coupled to a solid-state defect qubit. By ion implantation, the above solution can accurately control the positions and number of formed NV centers, to help control coupling between the solid-state defect qubit and the superconducting qubit. In this way, a superconducting qubit with a short coherence time can store information into a solid-state defect qubit with a long coherence time, so that a decoherence time of the information is increased, and an effective number of quantum computing operations are easier to achieve within the coherence time.
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公开(公告)号：EP4421672A1
公开(公告)日：2024-08-28
申请号：EP23845012.6
申请日：2023-05-18
发明人： MA, Shengming , CHEN, Yue , WANG, Jianming , HUAI, Sainan , ZHANG, Shengyu , WANG, Xuemeng , XU, Xiong , LI, Yanghepu
IPC分类号： G06F30/392
CPC分类号： G06F30/392 , G06F30/394
摘要： The present application discloses a chip layout wiring method and apparatus, a device, a storage medium and a chip layout, and relates to the technical field of chips. The method comprises: acquiring a chip layout to be wired, and wiring planning information corresponding to the chip layout; the wiring planning information comprising planning information for a first point location in the chip layout, the planning information of the first point location being used for defining a location area, wiring orientation, and planning track of the first point location, and a first end of the planning track being connected to the first point location (410); according to the location area and the wiring orientation, providing a second point location for connecting the chip layout, and a first wiring segment for a second end of the planning track (420); according to the planning track, arranging a second end connected to the planning track, and a second wiring segment of the first point location (430); and according to the first wiring segment and the second wiring segment, arranging connection wiring (440) between the second point location and the first point location. The present application can achieve automatic wiring and improves the accuracy of automatic wiring.
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公开(公告)号：EP4095605A1
公开(公告)日：2022-11-30
申请号：EP21838962.5
申请日：2021-09-08
发明人： ZHAO, Zhongping , ZHANG, Wenlong , DAI, Maochun , HUAI, Sainan , ZHOU, Yu
摘要： This application relates to a photoresist removal method and a photoresist removal system, and to the field of chip manufacturing technologies. The method includes: acquiring a target wafer, a photoresist being provided on a surface of the target wafer, a surface of a photoresist layer of the photoresist being plated with a metal overhead layer; immersing the target wafer in a first organic solvent at a first temperature in a water bath for a first duration; rinsing the target wafer with a new first organic solvent after the first duration; performing, in the first organic solvent, ultrasonic cleaning on the rinsed target wafer for a second duration based on a target ultrasonic power; removing the residual first organic solvent on the surface of the target wafer after the second duration; and drying the target wafer with the solvent removed by simultaneous centrifugal drying and gas purging to obtain the target wafer with the photoresist removed. Through the above method, the treatment effect of the photoresist is improved, and at the same time the product quality of the obtained metal devices is enhanced.
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公开(公告)号：EP4030469A1
公开(公告)日：2022-07-20
申请号：EP21815877.2
申请日：2021-09-28
申请人： Tencent Technology (Shenzhen) Company Limited , Suzhou Institute of Nano-tech and Nano-bionics (SINANO) Chinese Academy of Sciences
发明人： ZHANG, Wenlong , HUAI, Sainan , ZHENG, Yarui , FENG, Jiagui , XIONG, Kanglin , DING, Sunan
IPC分类号： H01L21/768 , H01L21/764
摘要： This application discloses a method for fabricating an air bridge, an air bridge structure, and a superconducting quantum chip, and relates to the field of circuit structures. The method includes: depositing a bridge brace material defining a shape of the air bridge on a substrate; coating a patterned photoresist on the substrate and the bridge brace material; performing exposure patterning treatment on the patterned photoresist based on an opening requirement of the air bridge, the opening requirement being used for indicating a position requirement of an opening on a deck of the air bridge; developing the exposure patterning-treated patterned photoresist; and depositing a bridge material on the developed bridge brace material, to obtain the air bridge having the opening. By performing exposure patterning treatment on a patterned photoresist, an opening structure running through a deck is arranged on the deck. In the process of fabricating an air bridge, a bridge brace material is released through the opening structure, and an etching material is released from a position of an opening to etch the bridge brace material. Therefore, the complete release of the bridge brace material is ensured, and bridge brace material residues are prevented from being left inside the bridge hole.
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10.发明公开
公开(公告)号：EP4012757A1
公开(公告)日：2022-06-15
申请号：EP21838964.1
申请日：2021-10-14
申请人： Tencent Technology (Shenzhen) Company Limited , Suzhou Institute of Nano-tech and Nano-bionics (SINANO) Chinese Academy of Sciences
发明人： ZHANG, Wenlong , YANG, Chuhong , HUAI, Sainan , ZHENG, Yarui , ZHANG, Shengyu , FENG, Jiagui , XIONG, Kanglin , WU, Biao , HUANG, Yongdan , CHEN, Xiao , DING, Sunan
IPC分类号： H01L21/768 , H01L21/02 , H01L21/3205
摘要： The invention discloses an air bridge structure and a manufacturing method thereof, and a superconducting quantum chip and a manufacturing method thereof. The manufacturing method for an air bridge structure includes: providing a substrate and forming a first photoresist structure on the substrate, the first photoresist structure including a first photoresist layer and a second photoresist layer and being provided with a first opening, and the first opening including a first sub-opening that runs through the second photoresist layer and that includes an undercut structure and a second sub-opening that runs through the first photoresist layer; depositing an inorganic bridge supporting material layer on the substrate on which the first photoresist structure is formed, and stripping the first photoresist structure to form a bridge supporting structure located at the first opening; forming a second photoresist structure on a side of the substrate on which the bridge supporting structure is formed, the second photoresist structure including a third photoresist layer and being provided with a second opening, the bridge supporting structure being located in the second opening, and the second opening being used for forming the air bridge structure; and depositing an air bridge material layer on the substrate on which the second photoresist structure is formed, stripping the second photoresist structure, and releasing the bridge supporting structure to obtain the air bridge structure.
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