公开(公告)号：EP3080844A1

公开(公告)日：2016-10-19

申请号：EP14869386.4

申请日：2014-12-12

申请人： Texas Instruments Incorporated

发明人： LIM, Kwan-Yong ,  BLATCHFORD, James, Walter ,  EKBOTE, Shashank, S. ,  CHOI, Younsung

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L27/092 ,  H01L21/76897 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/665 ,  H01L29/66636

摘要： An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.

摘要翻译： 在间隙中形成有与MOS晶体管邻接的MOS晶体管和与MOS晶体管相邻的场氧化物上的栅极结构和外延源极/漏极与场氧化物之间的间隙的集成电路。 在暴露的外延源/漏区上形成金属硅化物。 在集成电路上形成CESL，并且在CESL上形成PMD层。 通过PMD层和CESL形成接触以与外延源极/漏极区上的金属硅化物形成电连接。

公开(公告)号：EP3345219A1

公开(公告)日：2018-07-11

申请号：EP16843189.8

申请日：2016-09-06

申请人： Texas Instruments Incorporated

发明人： CHOI, Younsung ,  RILEY, Deborah, J.

IPC分类号： H01L27/06 ,  H01L21/8232

CPC分类号： H01L29/7848 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66492 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833

摘要： An integrated circuit and method having a first PMOS transistor with extension and pocket implants and with SiGe source and drains and having a second PMOS transistor without extension and without pocket implants and with SiGe source and drains. The distance from the SiGe source and drains to the gate of the first PMOS transistor is greater than the distance from the SiGe source and drains to the gate of the second PMOS transistor and the turn on voltage of the first PMOS transistor is at least 50 mV higher than the turn on voltage of the second PMOS transistor.

公开(公告)号：EP3036769A1

公开(公告)日：2016-06-29

申请号：EP14838365.6

申请日：2014-08-22

申请人： Texas Instruments Incorporated

发明人： EKBOTE, Shashank S. ,  LIM, Kwan-Yong ,  ESHUN, Ebenezer ,  CHOI, Younsung

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L29/45 ,  H01L21/28123 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

摘要： In described examples, an integrated circuit (100) includes semiconductor material (104). A first gate structure (108) includes a gate dielectric layer (112) and a gate (114). A second gate structure (118) includes a gate (122) that does not overlap a sidewall (142) of a field oxide (106). An SiGe source/drain region (138) is between the first and second gate structures (108, 118), such that a top edge (140) does not extend more than one third of a depth of the SiGe source/drain region (138) from a top surface of the semiconductor material (104). Dielectric spacers (124, 152) are adjacent to lateral surfaces of the gate (122), extending onto the SiGe source/drain region (138). A contact (160) is between the first and second gate structures (108, 118), such that at least half of a bottom of the contact (160) directly contacts metal silicide (156) on the SiGe source/drain region (138).

摘要翻译： 集成电路包括PMOS栅极结构和相邻场氧化物上的栅极结构。 在场氧化物上的栅极结构上形成外延硬掩模，使得外延硬掩模与PMOS源极/漏极区域中的半导体材料重叠。 SiGe半导体材料在源极/漏极区域中外延形成，使得在场氧化物处的SiGe半导体材料的顶部边缘不会延伸超过邻接该场的源极/漏极区域中的SiGe的深度的三分之一 氧化物。 场氧化物上的栅极结构的侧表面上的介电隔离物延伸到SiGe上; 至少有三分之一的SiGe被暴露。 金属硅化物覆盖SiGe的顶表面的至少三分之一。 触点具有至少一半的触点的底部直接接触SiGe上的金属硅化物。