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公开(公告)号：EP2391014A1
公开(公告)日：2011-11-30
申请号：EP10835733.6
申请日：2010-05-31
发明人： YASUDA Akira , OKAMURA Jun-ichi
CPC分类号： H03M1/066 , H03M1/74 , H03M3/502 , H04R3/00 , H04R2420/03
摘要： Provided is a selection device including an acquisition section for acquiring digital selection signals, and an output section for outputting selection signals to respective unit cells, each unit cell capable of being commanded to output the value zero. The selection device is characterized in that : each selection signal is for commanding the unit cell to output a value corresponding to that selection signal; the sum of the values to be output as commanded by the respective selection signals, which are output to the respective unit cells, is a value determined in association with the digital selection signal; and if the output corresponding to the digital selection signal is the value zero, then selection signals each commanding to output a non-zero value (N) are output to some of the unit cells.
摘要翻译： 提供了一种选择装置，其包括用于获取数字选择信号的获取部分和用于将选择信号输出到各个单位单元的输出部分，每个单位单元能够被命令输出值为零。 选择装置的特征在于：每个选择信号用于命令单位单元输出与该选择信号相对应的值; 输出到各个单位单元的由各个选择信号命令输出的值的和是与数字选择信号相关联地确定的值; 并且如果对应于数字选择信号的输出值为零，则每个命令输出非零值（N）的选择信号被输出到一些单位单元。
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公开(公告)号：EP2913931A1
公开(公告)日：2015-09-02
申请号：EP13848684.0
申请日：2013-10-25
发明人： YASUDA Akira , OKAMURA Jun-ichi
摘要： Provided is a data converter which is provided with a clock signal input part which inputs a clock signal, and an input part which inputs an input signal, a sampling part which, in response to the clock signal input to the clock signal input part, performs sampling of the input signal input to the input part, and a signal processing part which performs signal processing according to the sampling cycle and outputs an output signal, wherein when the cycle of the clock signal input to the clock signal input part becomes longer, the output signals output by the signal processing part are reduced.
摘要翻译： 提供一种数据转换器，其具有输入时钟信号的时钟信号输入部分和输入输入信号的输入部分;采样部分，其响应于输入到时钟信号输入部分的时钟信号执行 对输入到输入部分的输入信号进行采样;以及信号处理部分，其根据采样周期执行信号处理并输出输出信号，其中当输入到时钟信号输入部分的时钟信号的周期变长时， 由信号处理部分输出的输出信号被减少。
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公开(公告)号：EP2782361A1
公开(公告)日：2014-09-24
申请号：EP12843176.4
申请日：2012-10-25
发明人： YASUDA Akira , OKAMURA Jun-ichi
IPC分类号： H04R3/00
CPC分类号： H03F3/2175 , G06F17/3074 , H03F2200/331 , H04H20/88 , H04R1/005 , H04R3/00 , H04R9/063 , H04R27/00 , H04R2209/026 , H04R2209/041 , H04R2460/03
摘要： Provided is a digital acoustic system comprising: a ΔΣ modulator that modulates a digital input signal and outputs a digital signal; a post-filter that is connected to the ΔΣ modulator and which performs mismatch shaping to convert the digital signal; a parallel-serial converter that converts the digital signal converted by the post-filter into a digital signal which is serially transmitted; a serial-parallel converter that restores the digital signal converted by the parallel-serial converter; and a drive circuit which receives the digital signal restored by the serial-parallel converter, and drives drive elements to convert the signal into an analog audio signal.
摘要翻译： 提供了一种数字声学系统，包括：“£调制器，其调制数字输入信号并输出数字信号; 后滤波器，其连接到“£调制器并且执行失配整形以转换数字信号; 将由后置滤波器转换的数字信号转换成串行发送的数字信号的并行串行转换器; 并行转换器，用于恢复并行转换器转换的数字信号; 以及驱动电路，其接收由串并转换器恢复的数字信号，并驱动驱动元件将信号转换为模拟音频信号。
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公开(公告)号：EP2391014B1
公开(公告)日：2017-12-27
申请号：EP10835733.6
申请日：2010-05-31
发明人： YASUDA Akira , OKAMURA Jun-ichi
CPC分类号： H03M1/066 , H03M1/74 , H03M3/502 , H04R3/00 , H04R2420/03
摘要： Provided is a selection device including an acquisition section for acquiring digital selection signals, and an output section for outputting selection signals to respective unit cells, each unit cell capable of being commanded to output the value zero. The selection device is characterized in that : each selection signal is for commanding the unit cell to output a value corresponding to that selection signal; the sum of the values to be output as commanded by the respective selection signals, which are output to the respective unit cells, is a value determined in association with the digital selection signal; and if the output corresponding to the digital selection signal is the value zero, then selection signals each commanding to output a non-zero value (N) are output to some of the unit cells.
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公开(公告)号：EP2744223A1
公开(公告)日：2014-06-18
申请号：EP12824145.2
申请日：2012-08-09
发明人： YASUDA Akira , OKAMURA Jun-ichi
IPC分类号： H04R3/00 , H03K17/695 , H03M3/02
摘要： As one embodiment of the present invention, provided is a drive circuit to which a three-value signal including a value representing zero is input, and that outputs two two-value signals that drive two drive elements such that the difference between values representing the two two-value signals corresponds to a value representing the input three-value signal, the drive circuit being characterized by the combination of the output two two-value signals when the value of the input three-value signal represents zero being determined in accordance with the input history of the three-value signal. The drive circuit may also be provided with a memory that records a flag value that is reversed in accordance with the input history of the input three-value signal, and the combination of the output two two-value signals being determined in accordance with the flag.
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