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    A METHOD FOR GENERATION OF A PULSE PATTERN, AND A TRANSMITTER THEREFOR
    5.
    发明公开
    A METHOD FOR GENERATION OF A PULSE PATTERN, AND A TRANSMITTER THEREFOR 审中-公开
    VERFAHREN ZUR ERZEUGUNG EINES PULSMUSTERS UND SENDERDAFÜR

    公开(公告)号：EP3076547A1

    公开(公告)日：2016-10-05

    申请号：EP15305459.8

    申请日：2015-03-30

    Applicant: ALCATEL LUCENT

    Inventor： Haslach, Christoph ,  Markert, Daniel

    IPC: H03F3/217 ,  H03M3/00

    CPC classification number: H03F3/2175 ,  H03F3/2178 ,  H03F2200/331 ,  H03M3/35

    Abstract: The invention concerns a method for pulse pattern generation, wherein an input signal is duplicated into a first and a second input signal part, a delta sigma modulation of the first input signal part is performed resulting in a first modulated input signal part, a first pulse pattern part is generated from the first modulated input signal part, the second input signal part is multiplied with a factor resulting in a multiplied second input signal part, a delta sigma modulation of the multiplied second input signal part is performed resulting in a second modulated input signal part, a multiplied second pulse pattern part is generated from the second modulated input signal part by multiplication with the inverted factor, and the first pulse pattern part and the multiplied second pulse pattern part are added, and a transmitter therefor.

    Abstract translation: 本发明涉及一种用于脉冲模式生成的方法，其中将输入信号复制到第一和第二输入信号部分中，执行第一输入信号部分的ΔΣ调制，得到第一调制输入信号部分，第一脉冲 从第一调制输入信号部分生成图形部分，将第二输入信号部分乘以导致相乘的第二输入信号部分的因子，执行相乘的第二输入信号部分的ΔΣ调制，得到第二调制输入 信号部分，通过与反相因子相乘从第二调制输入信号部分产生相乘的第二脉冲图案部分，并且添加第一脉冲图案部分和相乘的第二脉冲图案部分，以及发射器。

    All digital zero-voltage switching
    6.
    发明公开
    All digital zero-voltage switching 有权
    全数字零电压开关

    公开(公告)号：EP2779443A2

    公开(公告)日：2014-09-17

    申请号：EP14158853.3

    申请日：2014-03-11

    Applicant: Analog Devices, Inc.

    Inventor： Schafferer, Bernd ,  Zhao, Bing

    IPC: H03F3/217 ,  H03F1/02 ,  H03F3/24 ,  H03F3/19

    CPC classification number: H03F1/0205 ,  H03F3/19 ,  H03F3/2175 ,  H03F3/2176 ,  H03F3/245

    Abstract: Power efficiency is an important design requirement of power amplifiers. To improve power efficiency, a solution proposed in this present disclosure includes an all-digital zero-voltage switching apparatus for directly driving a switching power amplifier through a desired current pulse shape. The apparatus includes a digital engine and a digital-to-analog converter (DAC). The digital engine processes baseband data and generates a digital output. The digital output of the digital engine drives the DAC to generate a digitally controlled current output having that desired current pulse shape. The digitally controlled current output is used to directly drive the switch power amplifier (704) to improve power efficiency. The digitally controlled current output comprising digitally generated current pulses is controlled accurately by the digital engine and the DAC, and thus allows the switching power amplifier (204) to operate optimally with higher power efficiency than conventional power amplifiers.

    Abstract translation: 功率效率是功率放大器的重要设计要求。 为了提高功率效率，本公开中提出的解决方案包括用于通过期望的电流脉冲形状来直接驱动开关功率放大器的全数字零电压开关装置。 该设备包括数字引擎和数字 - 模拟转换器（DAC）。 数字引擎处理基带数据并生成数字输出。 数字引擎的数字输出驱动DAC产生具有所需电流脉冲形状的数字控制电流输出。 数字控制的电流输出用于直接驱动开关功率放大器（704）以提高功率效率。 包括数字生成的电流脉冲的数字控制电流输出由数字引擎和DAC精确地控制，并且因此允许开关功率放大器（204）以比传统功率放大器更高的功率效率以最佳方式操作。

    AMPLIFIER ARRANGEMENT
    7.
    发明公开
    AMPLIFIER ARRANGEMENT 审中-公开
    放大器布置

    公开(公告)号：EP2735095A2

    公开(公告)日：2014-05-28

    申请号：EP12743928.9

    申请日：2012-07-17

    Applicant: KATHREIN-Werke KG

    Inventor： SCHMIDT, Lothar

    IPC: H03F1/02 ,  H03F3/217 ,  H03F3/60 ,  H03F3/72

    CPC classification number: H03F3/195 ,  H03F1/0277 ,  H03F1/0288 ,  H03F3/2175 ,  H03F3/602 ,  H03F3/72 ,  Y10T29/49117

    Abstract: An amplifier arrangement for amplifying a radio signal comprising at least a first amplifier module and a second amplifier module is presented wherein a splitter stage for dividing an amplifier stage input signal into several signal portions. The signal portions are amplified in the at least two parallel amplifier modules. A combiner stage combines the separate amplifier output signals into a single amplifier arrangement output signal.

    Abstract translation: 提出了一种用于放大无线电信号的放大器装置，其至少包括第一放大器模块和第二放大器模块，其中，分离器级用于将放大器级输入信号分成几个信号部分。 信号部分在至少两个并联放大器模块中被放大。 组合器级将单独的放大器输出信号组合成单个放大器布置输出信号。

    Power amplifier chain implementing a sigma-delta modulator with digital predistortion feedback
    9.
    发明公开
    Power amplifier chain implementing a sigma-delta modulator with digital predistortion feedback 有权
    功率放大器链实现具有数字预失真反馈的Σ-Δ调制器

    公开(公告)号：EP2403136A1

    公开(公告)日：2012-01-04

    申请号：EP10167761.5

    申请日：2010-06-29

    Applicant: Alcatel Lucent

    Inventor： Dartois, Luc

    IPC: H03F1/32 ,  H03F3/217 ,  H04B14/06

    CPC classification number: H03F3/2175 ,  H03F1/3247 ,  H04B14/064

    Abstract: The invention concerns a power amplifier chain (302, 306, 308, 310) aimed to feed a power amplifier (312) with a digital signal (303) generated by sigma-delta modulation means (102) associated with control means (314) based on a model of the power amplifier (312) in order to determine a control signal (307) controlling said sigma-delta modulation means and compensate a quantification treatment of said digital signal (303) by a quantizer (306), characterized in that it comprises control means (314) to operate a feedback loop on the sigma-delta modulation means (312) based on the signal (303) transmitted by the sigma-delta modulations means.

    Abstract translation: 本发明涉及一种功率放大器链（302,306,308,310），旨在向功率放大器（312）馈送基于与控制装置（314）相关联的基于Σ-Δ调制装置（102）的数字信号（303） 在功率放大器（312）的模型上，以便确定控制所述Σ-Δ调制装置并通过量化器（306）补偿所述数字信号（303）的量化处理的控制信号（307），其特征在于，它 包括控制装置（314），用于基于由所述Σ-Δ调制装置发送的信号（303）在所述Σ-Δ调制装置（312）上操作反馈回路。

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