公开(公告)号：EP4429118A1

公开(公告)日：2024-09-11

申请号：EP24159995.0

申请日：2024-02-27

Applicant: Avago Technologies International Sales Pte. Limited

Inventor： Ragab, Kareem ,  Lin, Xiaofeng ,  Cheung, Darwin ,  Mo, Chi ,  Chandrasekhar, Vinay ,  Song, Jungwoo ,  Jiang, Xicheng

IPC: H03M1/06 ,  H03M1/08 ,  H03M1/46 ,  H03M1/68 ,  H03M1/80 ,  H03M3/00

CPC classification number: H03M1/468 ,  H03M1/0854 ,  H03M1/687 ,  H03M1/804 ,  H03M1/066 ,  H03M1/0673 ,  H03M3/39 ,  H03M3/338 ,  H03M3/35 ,  H03M1/0678

Abstract: A device (e.g., SAR ADC device) include a DAC circuit and generates a digital output based on logic circuitry that includes SAR logic. Additional logic circuitry includes delta modulation circuitry and dynamic element matching circuitry. The delta modulation circuitry provides several digital outputs of the SAR DAC, while the dynamic element matching circuitry selects a different set of capacitors from the DAC circuit. Each cycle is added together and averaged, and then added to the digital output from the SAR logic.

公开(公告)号：EP3170029A2

公开(公告)日：2017-05-24

申请号：EP15826074.5

申请日：2015-06-17

Applicant: Cirrus Logic, Inc.

Inventor： MELANSON, John L. ,  SINGH, Rahul ,  DRAKSHAPALLI, Prashanth ,  BRUMMEL, Dale ,  HODAPP, Stephen T.

IPC: G01V1/00 ,  H03M3/04

CPC classification number: H03M3/424 ,  G01V1/181 ,  H03M1/066 ,  H03M3/388 ,  H03M3/454

Abstract: A low power analog-to-digital converter configured to sense sensor signals may include a loop filter and a feedback digital-to-analog converter. The loop filter may have a loop filter input configured to receive an input current signal from a sensor and generate an output signal responsive to the input current signal. The feedback digital-to-analog converter may have a feedback output configured to generate a current-mode or charge-mode feedback output signal responsive to the output signal, the feedback output coupled to the loop filter input in order to combine the input current signal and the feedback output signal at the input.

Abstract translation: 配置为感测传感器信号的低功率模数转换器可以包括环路滤波器和反馈数模转换器。 环路滤波器可以具有环路滤波器输入，其被配置为从传感器接收输入电流信号，并响应于输入电流信号产生输出信号。 反馈数模转换器可以具有被配置为响应于输出信号产生电流模式或电荷模式反馈输出信号的反馈输出，反馈输出耦合到环路滤波器输入，以便组合输入电流信号 和输入端的反馈输出信号。

公开(公告)号：EP3044796A1

公开(公告)日：2016-07-20

申请号：EP14776934.3

申请日：2014-09-09

Applicant: Microchip Technology Incorporated

Inventor： MEACHAM, Daniel, R. ,  PANIGADA, Andrea ,  SHIH, David

IPC: G11C27/02 ,  H03M1/12 ,  H03M1/06

CPC classification number: H03M1/08 ,  G11C27/02 ,  G11C27/024 ,  H03M1/066 ,  H03M1/1033 ,  H03M1/12 ,  H03M1/1205 ,  H03M1/122 ,  H03M1/1225 ,  H03M1/167 ,  H03M1/36

Abstract: An analog input stage has m differential input channels, wherein m>l. The analog input stage is configured to select one of the m differential input channels and provide an output signal. The analog input stage has n identical selection units each having m differential channel inputs and one differential output, wherein n is at least 2111"1. Each selection unit is operable to be coupled to any of the differential input channels through respective differential multiplexer units, wherein the multiplexor units are driven to select one of the differential input channels and couple the selected differential channel input through a butterfly switch unit with the differential output of the selection unit. The differential output signals of the n selection units are combined whereby unwanted crosstalk from channels other than a selected channel are removed by cancellation.

Abstract translation: 模拟输入级具有m个差分输入通道，其中m> 1。 模拟输入级被配置为选择m个差分输入通道之一并提供输出信号。 模拟输入级具有n个相同的选择单元，每个具有m个差分通道输入和一个差分输出，其中n至少为2m-1。 每个选择单元可操作以通过相应的差分多路复用器单元耦合到任何差分输入通道，其中多路复用器单元被驱动以选择差分输入通道中的一个，并通过蝶形开关单元将所选择的差分通道输入与差分 输出选择单元。 组合n个选择单元的差分输出信号，从而通过取消消除了除了所选频道之外的信道的不希望的串扰。

公开(公告)号：EP3021489A1

公开(公告)日：2016-05-18

申请号：EP15194532.6

申请日：2015-11-13

Applicant: Analog Devices, Inc.

Inventor： Devarajan, Siddharth ,  Singer, Lawrence ,  Shrestha, Prawal Man ,  Huang, Pingli

IPC: H03M1/12 ,  H03M1/06 ,  H03M1/10

CPC classification number: H03M1/121 ,  H03M1/00 ,  H03M1/0604 ,  H03M1/0607 ,  H03M1/0609 ,  H03M1/0612 ,  H03M1/066 ,  H03M1/0836 ,  H03M1/1033 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/124

Abstract: A time-interleaved analog-to-digital converter (ADC) uses M sub-analog-to-digital converters (sub-ADCs) to, according to a sequence, sample an analog input signal to produce digital outputs. When the M sub-ADCs are interleaved, the digital outputs exhibit mismatch errors between the M sub-ADCs due to mismatches between the sub-ADCs. A more second order subtle effect is that the mismatch error for a particular digital output from a particular ADC, due to internal coupling or other such interaction and effects between the M sub-ADCs, can vary depending on which sub-ADC(s) were used before and/or after the particular sub-ADC. If M sub-ADCs are time-interleaved randomly, the mismatches between the M sub-ADCs become a function of the sub-ADC selection pattern in the sequence. The present disclosure describes mechanisms for measuring and reducing these order-dependent mismatches to achieve high dynamic range performance in the time-interleaved ADC.

Abstract translation: 时间交错模拟数字转换器（ADC）使用M个子模拟 - 数字转换器（子ADC），其中，根据一个序列，采样模拟输入信号以产生数字输出。 当M个子ADC被交错，所述M个子ADC之间由于子ADC之间的失配的数字输出呈现的失配误差。 更二阶微妙效果做了失配误差从特定ADC特定数字输出，由于内部耦合或其他搜索相互作用和M个子ADC之间效果可以变化，这取决于子ADC（S）是 之前和/或所述特定子ADC后使用。 如果M个子ADC是时间交织随机地，将所述M个子ADC之间的失配变得序列中的子ADC选择模式的功能。 本公开描述了用于测量和减少合成顺序依赖性的失配，以实现在时间交织ADC的高动态范围的性能的机制。

公开(公告)号：EP2156562B1

公开(公告)日：2012-07-11

申请号：EP08763118.0

申请日：2008-05-27

Applicant: NXP B.V.

Inventor： DORIS, Konstantinos

IPC: H03M1/06 ,  H03M1/12

CPC classification number: H03M1/0678 ,  H03M1/066 ,  H03M1/1215

Abstract: The present invention relates to a signal processing apparatus comprising a signal input and a signal output; a plurality of signal processing units, wherein each signal processing unit having the same structure and at least one spatial error, being connected to the signal input, and being adapted to subject an input signal from the signal input to predetermined signal processing; selection means configured to select and form a predetermined number of groups from the plurality of signal processing units in accordance with a predetermined criterion; and control means for controlling the groups of the signal processing units to be active in a time interleaved schema, wherein an active group provides a respective processed input -signal as an output signal to the signal output; wherein the plurality of signal processing units comprises more signal processing units as required to realize a predetermined time interleaving factor.

公开(公告)号：EP1522145A1

公开(公告)日：2005-04-13

申请号：EP02740017.5

申请日：2002-07-05

Applicant: Raytheon Company

Inventor： COSAND, Albert E.

IPC: H03M1/06

CPC classification number: H03M1/066 ,  H03M1/361 ,  H03M3/424 ,  H03M3/464

Abstract: A quantizer adapted for use with a delta-sigma analog-to-digital converter. The quantizer includes first and second comparators adapted to compare an input analog signal to a threshold and provide a digital output in response thereto. First and second thresholds are provided to the first and second comparators respectively. In accordance with the present teachings, a mechanism is provided for changing the thresholds to minimize conversion errors. While the mechanism for changing the thresholds may be implemented with resistive and/or capacitive ladders, in the illustrative embodiment, digital-to-analog converters are utilized. The DACs are driven by error shaping logic. The inventive quantizer allows for an improved delta-sigma analog-to-digital converter design which combines an ADC and a DAC. The DAC reconstructs the analog equivalent of the digital output of the ADC. The ADC is a flash converter consisting of one comparator per threshold. The DAC operates by summing the outputs of a set of nominally identical unit elements. The DAC has the same number of elements as there are comparators in the flash ADC and each comparator drives one element of the DAC. A novel feature is that the thresholds of the comparators in the ADC can individually be dynamically adjusted, so that the correspondence between an element of the DAC and a particular threshold of the ADC can be varied from sample to sample under the control of logic circuitry. This arrangement allows the correspondence between DAC elements and ADC thresholds to be remapped without introducing any additional delay into the signal path between the ADC and the DAC. In a high speed continuous-time delta sigma modulator, this allows randomization or shaping of the mismatch errors of the DAC elements to be achieved without incurring any penalty in sample rate, nor adding any excess delay into the loop that might destabilize or otherwise degrade the operation of the modulator.

公开(公告)号：EP1134899A3

公开(公告)日：2004-01-07

申请号：EP01106569.5

申请日：2001-03-15

Applicant: Burr-Brown Japan, Ltd.

Inventor： Nakao, Shigetoshi ,  Hamasaki, Toshihiko

IPC: H03M1/68 ,  H03M3/04

CPC classification number: H03M1/68 ,  H03M1/066 ,  H03M3/502 ,  H03M7/3004

Abstract: A digital-to-analog converter is provided for accomplishing analog output characteristics using different digital-to-analog conversion type digital signal processing schemes. A plurality of bits of a received digital signal are divided into a plurality of bit groups. A digital signal processing unit includes a plurality of bit group digital signal processors for receiving the plurality of bit groups. The plurality of digital signal processors employ one or more digital-to-analog conversion type digital signal processing schemes for generating a plurality of digital signal processed outputs. The converter adds the plurality of digital signal processed outputs to generate a composite signal processed output, and includes a weight generating unit for controlling a plurality of shared weight generating elements in response to the composite digital signal processed output to generate an analog output signal.

Abstract translation: 一种数字 - 模拟转换器被设置用于使用不同的数字 - 模拟转换型数字信号处理方案实现模拟输出特性。 接收的数字信号的位数的多个被划分成比特组的复数。 一种数字信号处理单元包括位组的数字信号处理器，用于接收比特组的多个A多元性。 数字信号处理器的多元性可采用一个或多个数字到模拟转换型数字信号处理方案，用于生成数字信号处理的输出的复数。 该转换器增加了数字信号处理的输出的多元化，以产生一个复合信号处理后的输出，并包括权重生成单元，用于控制共享权重生成响应于所述复合数字信号处理后的输出元件在模拟输出信号，以生成的复数。

公开(公告)号：EP0142182B1

公开(公告)日：1991-04-24

申请号：EP84201304.7

申请日：1984-09-11

Applicant: Philips Patentverwaltung GmbH ,  Philips Electronics N.V.

Inventor： Demmer, Walter Heinrich

IPC: H03M1/74

CPC classification number: H03M1/066 ,  H03M1/808

公开(公告)号：EP3280055A1

公开(公告)日：2018-02-07

申请号：EP17182826.2

申请日：2017-07-24

Applicant: MediaTek Inc.

Inventor： WENG, Chan-Hsiang ,  LO, Tien-Yu

IPC: H03M3/04 ,  H03M1/06

CPC classification number: H03M3/426 ,  H03M1/00 ,  H03M1/066 ,  H03M1/12 ,  H03M3/30 ,  H03M3/428 ,  H03M3/436 ,  H03M3/454

Abstract: A delta-sigma modulator includes a receiving circuit, a loop filter module, a quantizer, a delta-sigma truncator, a digital filter module, and an output circuit. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter module is arranged for filtering the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a first digital signal according to the filtered summation signal. The delta-sigma truncator is arranged for truncating the first digital signal to generate a second digital signal. The digital filter module is arranged for filtering the first digital signal and the second digital signal to generate a filtered first digital signal and a filtered second digital signal, respectively. The output circuit is arranged for generating an output signal according to the filtered first digital signal and the filtered second digital signal.

Abstract translation: Δ-Σ调制器包括接收电路，环路滤波器模块，量化器，Δ-Σ截断器，数字滤波器模块和输出电路。 接收电路被设置用于接收反馈信号和输入信号以生成求和信号。 环路滤波器模块用于对求和信号进行滤波以产生滤波后的和信号。 量化器用于根据滤波后的和信号生成第一数字信号。 Δ-Σ截断器被设置用于截断第一数字信号以产生第二数字信号。 数字滤波器模块用于对第一数字信号和第二数字信号进行滤波，以分别生成滤波后的第一数字信号和滤波后的第二数字信号。 输出电路用于根据滤波后的第一数字信号和滤波后的第二数字信号生成输出信号。

公开(公告)号：EP3158646A1

公开(公告)日：2017-04-26

申请号：EP15809124.9

申请日：2015-06-19

Applicant: HRL Laboratories, LLC

Inventor： XU, Zhiwei A. ,  BARINGER, Cynthia D. ,  PETRE, Peter ,  HITKO, Donald A. ,  COSAND, Albert

IPC: H03M3/02

CPC classification number: H03M3/47 ,  H03M1/066 ,  H03M3/358 ,  H03M3/37 ,  H03M3/454 ,  H03M3/46

Abstract: A delta sigma modulator which has improved the dynamic range. The ΔΣ modulator has a plurality of ADCs and a plurality of DACs, the plurality of ADCs and DACs are connected in a loop. The plurality of ADCs are coupled with an incoming analog signal. A clock generator provides a plurality of clock signals which control the plurality of ADCs and the plurality of DACs, the clock signals being offset relative to each other in the time domain thereby enabling each ADC in the plurality of ADCs one at a time and each DAC in the plurality of DACs one at a time so that the ΔΣ modulator processes data in the incoming analog signal in an interleaved fashion. The delta sigma modulator has an Nth order filter in a forward path of the loop.

Abstract translation: 一种增加动态范围的Δ-Σ调制器。 ΔΣ调制器具有多个ADC和多个DAC，多个ADC和DAC连接成一个环路。 多个ADC与输入的模拟信号耦合。 时钟发生器提供控制多个ADC和多个DAC的多个时钟信号，时钟信号在时域中彼此相对偏移，从而使得多个ADC中的每个ADC一次一个，并且每个DAC 在多个DAC中一次一个，使得ΔΣ调制器以交错方式处理输入模拟信号中的数据。 Δ-Σ调制器在环路的正向路径中具有N阶滤波器。