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    RANDOM CODE GENERATOR
    4.
    发明公开
    RANDOM CODE GENERATOR 审中-公开

    公开(公告)号：EP3512157A1

    公开(公告)日：2019-07-17

    申请号：EP19150919.9

    申请日：2019-01-09

    申请人： eMemory Technology Inc.

    发明人： WU, Meng-Yi ,  CHEN, Hsin-Ming

    IPC分类号： H04L9/08

    摘要： A random code generator includes an address Y decoder, an address X decoder, a PUF entropy pool, a processing circuit and an entropy key storage circuit. The address Y decoder includes plural Y control lines. The address Y decoder selectively activates the plural Y control lines according to a first address Y signal. The address X decoder includes plural X control lines. The address X decoder selectively activates the plural X control lines according to a first address X signal. The PUF entropy pool generates an output data according to the activated Y control lines and the activated X control lines. When the random code generator is in a normal working state, the processing circuit processes the output data into a random code according to at least one entropy key from the entropy key storage circuit.

    ANTIFUSE OTP MEMORY CELL WITH SELECT TRANSISTOR HAVING TWO GATE OXIDE THICKNESSES
    5.
    发明公开
    ANTIFUSE OTP MEMORY CELL WITH SELECT TRANSISTOR HAVING TWO GATE OXIDE THICKNESSES 审中-公开
    抗体 - OTP-SPEICHERZELLE麻省理工大学麻醉药ZWEI GATEOXIDDICKEN

    公开(公告)号：EP3139408A1

    公开(公告)日：2017-03-08

    申请号：EP16186237.0

    申请日：2015-03-19

    申请人： eMemory Technology Inc.

    发明人： WU, Meng-Yi ,  CHEN, Hsin-Ming ,  LU, Chun-Hung

    IPC分类号： H01L27/112 ,  H01L23/525 ,  H01L29/93 ,  G11C17/16 ,  H01L29/423

    摘要： An OTP memory cell including an antifuse unit (232) and a select transistor (234) is provided. The antifuse unit includes an antifuse layer (210) and an antifuse gate (212) disposed on a substrate in sequence, a modified extension doped region (214) disposed in the substrate below the antifuse layer, and a first doped region (216) and a second doped region (218) disposed in the substrate at two opposite sides of the antifuse gate. The doped regions, the antifuse layer and the antifuse gate form a varactor. The select transistor includes a select gate (220), a gate dielectric layer (222), the second doped region, and a third doped region (224). The thickness (D1) of the gate dielectric layer close to the second doped region is greater than the thickness (D2) of the gate dielectric layer close to the third doped region.

    摘要翻译： 提供了包括反熔丝单元（232）和选择晶体管（234）的OTP存储单元。 反熔丝单元包括依次设置在基板上的反熔丝层（210）和反熔丝栅极（212），设置在反熔丝层下方的基板中的改进的扩展掺杂区域（214）和第一掺杂区域（216）和 第二掺杂区域（218），设置在反熔丝闸门的两个相对侧的基板中。 掺杂区域，反熔丝层和反熔丝栅极形成变容二极管。 选择晶体管包括选择栅极（220），栅极介电层（222），第二掺杂区域和第三掺杂区域（224）。 靠近第二掺杂区域的栅极电介质层的厚度（D1）大于靠近第三掺杂区域的栅极电介质层的厚度（D2）。

    ENTANGLEMENT AND RECALL SYSTEM USING PHYSICALLY UNCLONABLE FUNCTION TECHNOLOGY
    7.
    发明公开
    ENTANGLEMENT AND RECALL SYSTEM USING PHYSICALLY UNCLONABLE FUNCTION TECHNOLOGY 审中-公开

    公开(公告)号：EP3512156A1

    公开(公告)日：2019-07-17

    申请号：EP19150732.6

    申请日：2019-01-08

    申请人： eMemory Technology Inc.

    发明人： WU, Meng-Yi ,  WANG, Chih-Min ,  CHEN, Hsin-Ming

    IPC分类号： H04L9/08 ,  H04L9/06

    摘要： An entanglement and recall system includes an antifuse-type PUF cell array and a processing circuit. The antifuse-type PUF cell array generates at least one key. The processing circuit is connected with the antifuse-type PUF cell array to receive the at least one key. While an entanglement action is performed, the processing circuit receives a plain text and the at least one key and generates a cipher text according to the plain text and the at least one key. While a recall action is performed, the processing circuit receives the cipher text and the at least one key and generates the plain text according to the cipher text and the at least one key.

    ANTIFUSE PHYSICALLY UNCLONABLE FUNCTION UNIT AND ASSOCIATED CONTROL METHOD
    8.
    发明公开
    ANTIFUSE PHYSICALLY UNCLONABLE FUNCTION UNIT AND ASSOCIATED CONTROL METHOD 审中-公开
    一种物理无关的函数单元及其控制方法

    公开(公告)号：EP3309790A1

    公开(公告)日：2018-04-18

    申请号：EP17195951.3

    申请日：2017-10-11

    申请人： eMemory Technology Inc.

    发明人： WU, Meng-Yi ,  CHEN, Hsin-Ming

    IPC分类号： G11C17/16 ,  H04L9/32

    CPC分类号： H04L9/3278 ,  G11C17/16 ,  G11C17/18

    摘要： An antifuse physically unclonable function (PUF) unit includes a first sub-antifuse cell, a second sub-antifuse cell, a connection circuit, a first copying circuit and a first reading circuit. The first sub-antifuse cell includes a first antifuse transistor. The second sub-antifuse cell includes a second antifuse transistor. The connection circuit is connected between a source/drain terminal of the first antifuse transistor and a source/drain terminal of the second antifuse transistor. The first copying circuit is connected with the first sub-antifuse cell, and includes a third antifuse transistor. The first reading circuit is connected with the first copying circuit. Moreover, the first reading circuit generates a random code according to a state of the third antifuse transistor.

    摘要翻译： 反熔丝物理不可克隆功能（PUF）单元包括第一子反熔丝单元，第二子反熔丝单元，连接电路，第一复制电路和第一读取电路。 第一子反熔丝单元包括第一反熔丝晶体管。 第二子反熔丝单元包括第二反熔丝晶体管。 连接电路连接在第一反熔丝晶体管的源极/漏极端子与第二反熔丝晶体管的源极/漏极端子之间。 第一复制电路与第一子反熔丝单元连接，并且包括第三反熔丝晶体管。 第一读取电路与第一复制电路连接。 此外，第一读取电路根据第三反熔丝晶体管的状态产生随机码。

    ANTIFUSE-TYPE ONE TIME PROGRAMMING MEMORY CELL AND CELL ARRAY STRUCTURE WITH SAME
    9.
    发明公开
    ANTIFUSE-TYPE ONE TIME PROGRAMMING MEMORY CELL AND CELL ARRAY STRUCTURE WITH SAME 审中-公开

    公开(公告)号：EP4134959A1

    公开(公告)日：2023-02-15

    申请号：EP22160993.6

    申请日：2022-03-09

    申请人： eMemory Technology Inc.

    发明人： CHEN, Lun-Chun ,  CHEN, Jiun-Ren ,  HO, Ping-Lung ,  CHEN, Hsin-Ming

    IPC分类号： G11C17/16

    摘要： An antifuse-type one time programming memory cell includes a select device, a following device and an antifuse transistor. A first terminal of the select device is connected with a bit line. A second terminal of the select device is connected with a first node. A select terminal of the select device is connected with a word line. A first terminal of the following device is connected with the first node. A second terminal of the following device is connected with a second node. A control terminal of the following device is connected with a following control line. A first drain/source terminal of the antifuse transistor is connected with the second node. A gate terminal of the antifuse transistor is connected with an antifuse control line. A second drain/source terminal of the antifuse transistor is in a floating state.

    RANDOM CODE GENERATOR AND ASSOCIATED RANDOM CODE GENERATING METHOD
    10.
    发明公开
    RANDOM CODE GENERATOR AND ASSOCIATED RANDOM CODE GENERATING METHOD 审中-公开

    公开(公告)号：EP3454320A1

    公开(公告)日：2019-03-13

    申请号：EP18190627.2

    申请日：2018-08-24

    申请人： eMemory Technology Inc.

    发明人： WU, Meng-Yi ,  CHEN, Hsin-Ming

    IPC分类号： G09C1/00 ,  H04L9/08 ,  G06F21/86 ,  H04L9/32

    摘要： A random code generator is installed in a semiconductor chip and includes a PUF cell array, a control circuit and a verification circuit. The PUF cell array includes m×n PUF cells. The control circuit is connected with the PUF cell array. While a enroll action is performed, the control circuit enrolls the PUF cell array. The verification circuit is connected with the PUF cell array. While a verification action is performed, the verification circuit determines that p PUF cells of the PUF cell array are normal PUF cells and generates a corresponding a mapping information, wherein p is smaller than m×n. While the semiconductor chip is enabled, the control circuit reads states of the p normal PUF cells of the PUF cell array according to the mapping information and generates a random code according to the states.