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    TRANSMISSION APPARATUS, RECEPTION APPARATUS, TRANSMISSION-RECEPTION SYSTEM, AND IMAGE DISPLAY SYSTEM
    3.
    发明公开
    TRANSMISSION APPARATUS, RECEPTION APPARATUS, TRANSMISSION-RECEPTION SYSTEM, AND IMAGE DISPLAY SYSTEM 审中-公开

    公开(公告)号：EP2424153A4

    公开(公告)日：2017-12-20

    申请号：EP10767133

    申请日：2010-04-22

    申请人： THINE ELECTRONICS INC

    发明人： OZAWA SEIICHI ,  AKITA HIRONOBU

    IPC分类号： H04L7/04 ,  G09G3/20 ,  H04L7/00 ,  H04L25/03 ,  H04N5/66

    CPC分类号： H04L7/0008 ,  G09G3/3611 ,  G09G2310/08 ,  G09G2370/08 ,  H04L7/0091 ,  H04N5/12 ,  H04N5/66

    摘要： The present invention provides a transmission apparatus and a reception apparatus easy to sample data correctly by a clock in the reception apparatus. In a detection section 25 of a reception apparatus 20 n , based on data output from a sampler section 23, both or either of detection of a phase difference between data received by a data reception section 21 and a clock received by a clock reception section 22, and/or waveform distortion of this data is performed. A detection signal indicating a result of detection by the detection section 25 is transmitted to a transmission apparatus 10 by a detection signal transmission section 26. In the transmission apparatus 10, by a control section 15, based on the detection signal received by a detection signal reception section 14, both or either of control of adjustment of a phase between data transmitted by a data transmission section 11 and a clock transmitted by a clock transmission section 12, and/or adjustment of an amplitude of the data is performed.

    VIDEO SIGNAL TRANSMISSION DEVICE
    5.
    发明授权
    VIDEO SIGNAL TRANSMISSION DEVICE 有权
    视频信号传输设备

    公开(公告)号：EP2908536B1

    公开(公告)日：2017-05-10

    申请号：EP15162516.7

    申请日：2008-10-31

    申请人： Thine Electronics, Inc.

    发明人： Ozawa, Seiichi

    IPC分类号： H04N21/41 ,  G06F3/14 ,  G09G5/00 ,  H04N21/4363 ,  H04N21/4405 ,  H04N21/4408 ,  G09G3/20

    CPC分类号： H04N21/4408 ,  G06F3/14 ,  G09G3/2092 ,  G09G5/006 ,  G09G5/008 ,  G09G2370/10 ,  H04N21/4122 ,  H04N21/43632 ,  H04N21/4405

    摘要： A video transmission device 10 has: a packer 11 which receives a video signal, a sync signal, and a data-enable signal, and generates a plurality of packet signals by packetizing the video signal and the sync signal based on the data-enable signal and according to the number of bytes of a packet corresponding to the number of gradation bits of the video signal; an encode unit 15 which generates a plurality of encoded packet signals by encoding the plurality of packet signals; and a serializer 14 which generates a serial packet signal by parallel-serial converting the plurality of encoded packet signals. The packer 11 generates a control signal including a pulse with a pulse width corresponding to the number of bytes of the packet, and the encode unit 15 subjects a portion of the packet signals corresponding to the pulse in the control signal from the packer, to an encode process which is different from a process for the other portion.

    摘要翻译： 视频传输设备10具有：打包器11，其接收视频信号，同步信号和数据使能信号，并且通过基于数据使能信号打包视频信号和同步信号来产生多个分组信号 并根据与视频信号的灰度位数相对应的数据包的字节数; 编码单元15，其通过对多个分组信号进行编码来生成多个编码分组信号; 以及串行器14，其通过并行 - 串行转换多个编码分组信号来产生串行分组信号。 打包器11生成包括具有与分组的字节数相对应的脉冲宽度的脉冲的控制信号，并且编码单元15使与来自打包器的控制信号中的脉冲相对应的一部分分组信号经历 编码过程与另一部分的过程不同。

    TRANSMISSION DEVICE, RECEPTION DEVICE, AND TRANSMISSION/RECEPTION SYSTEM
    6.
    发明公开
    TRANSMISSION DEVICE, RECEPTION DEVICE, AND TRANSMISSION/RECEPTION SYSTEM 审中-公开
    SENDEVORRICHTUNG，EMPFANGSVORRICHTUNG UND SENDE- / EMPFANGSSYSTEM

    公开(公告)号：EP3133823A1

    公开(公告)日：2017-02-22

    申请号：EP15779958.6

    申请日：2015-03-11

    申请人： Thine Electronics, Inc.

    发明人： TAKEUCHI, Ryo ,  MIURA, Satoshi

    IPC分类号： H04N21/436 ,  H04L7/08

    CPC分类号： H04L7/08 ,  G09G5/006 ,  G09G5/18 ,  G09G2340/02 ,  G09G2370/04 ,  G09G2370/10 ,  H04N5/04 ,  H04N21/23602 ,  H04N21/4342 ,  H04N21/436

    摘要： A transmission/reception system 1 includes a transmission device 10 configured to transmit image data and a reception device 20 configured to receive the image data transmitted from the transmission device 10. The transmission device 10 includes a serializer 11, an encoding unit 12, a data buffering unit 13, a data selection unit 14, a counter 15, and a synchronization signal generation unit 16. The data buffering unit 13 buffers data every n bits in synchronization with the clock. The data selection unit 14 outputs m-bit data selected from the data buffered by the data buffering unit 13 on the basis of a count value from the counter 15.

    摘要翻译： 发送/接收系统1包括被配置为发送图像数据的发送设备10和被配置为接收从发送设备10发送的图像数据的接收设备20.发送设备10包括串行器11，编码单元12，数据 缓冲单元13，数据选择单元14，计数器15和同步信号生成单元16.数据缓冲单元13与时钟同步地每n位缓冲数据。 数据选择单元14基于来自计数器15的计数值输出从数据缓冲单元13缓冲的数据中选择的m位数据。

    RECEPTION APPARATUS
    9.
    发明公开
    RECEPTION APPARATUS 审中-公开
    接收装置;

    公开(公告)号：EP2166695A4

    公开(公告)日：2012-10-10

    申请号：EP08711035

    申请日：2008-02-08

    申请人： THINE ELECTRONICS INC

    发明人： OMOTE KAZUYUKI ,  SAITO RYUTARO

    IPC分类号： H04L7/02 ,  H03L7/00

    CPC分类号： H03L7/07 ,  H03L7/0812 ,  H04L7/0008 ,  H04L7/0337

    摘要： In a reception apparatus 1, a multiphase sampling clock signal is generated by a sampling clock signal generation circuit 40, based on a clock signal which has been phase-adjusted by a phase adjustment circuit 50. The data of each of the bits of a serial data signal is sampled and output by a sampler block circuit 30n, with timing indicated by the sampling clock signal. The amount of phase adjustment of the clock signal in the phase adjustment circuit 50 is set such that the delay time from generation of the multiphase sampling clock signal in the sampling clock signal generation circuit 40 until indication of the sampling timing by the sampling clock signal in the sampler block circuit 30n is canceled.

    CLOCK DATA RESTORATION DEVICE
    10.
    发明公开
    CLOCK DATA RESTORATION DEVICE 审中-公开
    TAKTDATEN-WIEDERHERSTELLUNGSVORRICHTUNG

    公开(公告)号：EP2458773A1

    公开(公告)日：2012-05-30

    申请号：EP10802201.3

    申请日：2010-07-14

    申请人： Thine Electronics, Inc.

    发明人： OZAWA Seiichi ,  YAMAMOTO Shuhei

    IPC分类号： H04L7/033 ,  H03L7/08 ,  H03L7/093

    CPC分类号： H04L7/033 ,  H03L7/0891

    摘要： A clock data restoration device (1A) includes a sampler portion (11), a phase comparison portion (12), a drive portion (13), a charge pump (14), a capacitive element (15), a potential adjustment portion (16) and a voltage control oscillator (17). The phase comparison portion (12) outputs a signal (UP) that becomes a significant value when the phase of a clock (CKX) delays with respect to an input digital signal, and outputs a signal (DN) that becomes a significant value when the phase advances. The drive portion (13) increases or decreases a value δ to or from a variable Δ when the signals (UP) and (DN) become a significant value, and increases or decrease a value N to or from the variable Δ when the value of the variable Δ is equal to or more than +N or when the value of the variable Δ is equal to or less than -N, and signals (UPFRQ) and (DNFRQ) are output to the charge pump (14). The potential adjustment portion (16) increases or decreases a potential at a first end of a capacitive element (15) based on the signals (UP) and (DN).

    摘要翻译： 时钟数据恢复装置（1A）包括取样器部分（11），相位比较部分（12），驱动部分（13），电荷泵（14），电容元件（15），电位调节部分 16）和压控振荡器（17）。 当相位相对于输入数字信号延迟时钟（CKX）的相位时，相位比较部分（12）输出成为有效值的信号（UP），并输出当 阶段进展。 当信号（UP）和（DN）变为有效值时，驱动部分（13）增加或减少值“或从变量”增加或减少值“，当值” 变量“等于或大于+ N或当变量的值”等于或小于-N时，信号（UPFRQ）和（DNFRQ）被输出到电荷泵14。 电位调整部（16）基于信号（UP）和（DN）增大或减小电容元件（15）的第一端的电位。