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26 条记录 (耗时 0.012 秒)

    SYSTEMS AND METHODS PROVIDING MULTI-PATH LOW NOISE AMPLIFIERS WITH SEAMLESS SWITCHING
    2.
    发明公开
    SYSTEMS AND METHODS PROVIDING MULTI-PATH LOW NOISE AMPLIFIERS WITH SEAMLESS SWITCHING 审中-公开
    系统和方法与无缝切换的多路径低噪声放大器

    公开(公告)号：EP2510626A4

    公开(公告)日：2013-12-25

    申请号：EP10836482

    申请日：2010-12-06

    申请人： ZORAN CORP

    发明人： STEVENSON JAN-MICHAEL

    IPC分类号： H04B1/06

    CPC分类号： H03F1/0277 ,  H03F1/0261 ,  H03F3/195 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/294 ,  H03F2200/336 ,  H03F2200/375 ,  H03F2200/411 ,  H03F2200/432 ,  H03F2200/451 ,  H03G3/3068

    摘要： Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.

    MULTIMODE FILTER ARCHITECTURE
    3.
    发明公开
    MULTIMODE FILTER ARCHITECTURE 有权
    多模式滤波器架构

    公开(公告)号：EP2510628A4

    公开(公告)日：2012-11-28

    申请号：EP10836486

    申请日：2010-12-06

    申请人： ZORAN CORP

    发明人： LAURENT-MICHEL STEPHANE ,  SKULL OLIVER ,  DOAK ALAN

    IPC分类号： H04B1/10 ,  H04N5/455 ,  H04N5/46

    CPC分类号： H04N5/455 ,  H04B1/001 ,  H04N5/46 ,  H04N21/42638 ,  H04N21/4382 ,  H04N21/6112

    摘要： Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.

    MEMORY UTILIZATION FOR VIDEO DECODING AND DISPLAY WITH 3:2 PULL-DOWN
    5.
    发明公开
    MEMORY UTILIZATION FOR VIDEO DECODING AND DISPLAY WITH 3:2 PULL-DOWN 失效
    使用视频解码和显示单元3内存：2短路比

    公开(公告)号：EP0795251A4

    公开(公告)日：1998-03-18

    申请号：EP95939763

    申请日：1995-11-03

    申请人： ZORAN CORP

    发明人： CISMAS SORIN C

    IPC分类号： H04N7/01 ,  H04N7/26 ,  H04N7/50 ,  H04N7/00

    CPC分类号： H04N19/427 ,  H04N19/423 ,  H04N19/44 ,  H04N19/61

    摘要： A system and method for decoding a video bitstream and displaying the video with 3:2 pull-down using a frame buffer whose size is not sufficient to hold an entire decoded frame. This is accomplished by using the additional time required by the display with 3:2 pull-down to decode a portion of the frame for a second time. The present invention provides memory savings, additional flexibility in decoder design, and reductions in memory controller complexity and power consumption. In the case of MPEG-2 decoders, the present invention allows the implementation of PAL/SECAM main profile at main level decoders with 3:2 pull-down using only a 16 megabit memory.

    BROADBAND TUNER FOR VERY WIDE SIGNAL CONVERSION
    6.
    发明公开
    BROADBAND TUNER FOR VERY WIDE SIGNAL CONVERSION 审中-公开
    宽带调谐器很宽的信号转换

    公开(公告)号：EP2263320A4

    公开(公告)日：2014-07-09

    申请号：EP09729388

    申请日：2009-02-10

    申请人： ZORAN CORP

    发明人： RITCHEY CAREY ,  BEUMER KIM E ,  POP MARIUS

    IPC分类号： H04B1/26 ,  H03D7/16 ,  H04B1/00 ,  H04B15/06

    CPC分类号： H03D7/161 ,  H04B1/0035 ,  H04B1/28

    摘要： An agile RF tuner circuit capable of converting a wide portion of RF signal into an IF signal suitable for analog-to-digital conversion. The circuit up converts a received RF signal to a high IF signal and then down converts the high IF signal to a low IF signal. Embodiments of the RF circuit incorporate harmonic reject mixers to suppress harmonies and intermodulations typically associated with the frequency conversion process.

    PICTURE AND VIDEO STORAGE MANAGEMENT SYSTEM AND METHOD
    8.
    发明公开
    PICTURE AND VIDEO STORAGE MANAGEMENT SYSTEM AND METHOD 审中-公开
    系统和方法用于管理图像和视频商店

    公开(公告)号：EP1244999A4

    公开(公告)日：2006-04-12

    申请号：EP00980310

    申请日：2000-11-08

    申请人： ZORAN CORP

    发明人： CASTOR JON S ,  CHUI CHARLES K

    IPC分类号： H04N5/225 ,  G06T9/00 ,  H04N5/907 ,  H04N5/91 ,  H04N5/92 ,  H04N7/26 ,  H04N7/30 ,  H04N101/00 ,  G06K9/36 ,  G06K9/46

    CPC分类号： H04N19/61 ,  H04N19/115 ,  H04N19/129 ,  H04N19/146 ,  H04N19/63

    摘要： An image processing system (100) stores image files in a memory device (108) at a number of incremental quality levels. Each image file has an associated image quality (that is fidelity or resolution) level corresponding to a quality level at which the corresponding image has been encoded. The images are initially encoded by applying a predefined transform, such as a DCT transform or wavelet-like transform (200), to image data received from an image capture mechanism (102) and then applying a data compression method to the transform data (200). The image is regenerated by successively applying a data decompression method and an inverse transform to an image file (202). Image file size reduction circuitry (212) and one or more state machines are used to lower the quality level of a specified one of the image files, including circuitry for extracting a subset of the data in the specified image file and forming a lower quality version of the specified image file that occupies less space in the memory device than was previously occupied by the specified image data structure. As a result, the amount of space occupied by image files in the memory device can be reduced so as to make room for the storage of additional image files or to allow more rapid transmission in a restricted bandwidth environment.