公开(公告)号：EP0309302B1

公开(公告)日：1995-12-13

申请号：EP88401830.0

申请日：1988-07-13

申请人： AUTOMATED PROCESS CONTROL, INC.

发明人： Riley, Robert E., Jr.

IPC分类号： G08C15/12 ,  H02P7/00 ,  B60R16/02

CPC分类号： G05B19/07 ,  G05B19/042 ,  G05B2219/21037 ,  G05B2219/21038 ,  G05B2219/24061 ,  G05B2219/25051 ,  G05B2219/25314 ,  G05B2219/25315 ,  G05B2219/25324 ,  G05B2219/25333 ,  G08C15/12 ,  H04L7/0008

公开(公告)号：EP0711478B1

公开(公告)日：2001-09-12

申请号：EP94922586.6

申请日：1994-07-18

申请人： SQUARE D COMPANY

发明人： BURKE, George, Edmund, Jr. ,  HORNE, George, Marshall ,  CARTER, Michael, Baron

IPC分类号： H04J3/04 ,  G05B19/07 ,  G05B19/042

CPC分类号： G08C15/06 ,  G05B19/0423 ,  G05B19/07 ,  G05B2219/21037 ,  G05B2219/25051 ,  G05B2219/25315 ,  G05B2219/25321 ,  G05B2219/25324 ,  G05B2219/25333 ,  G05B2219/25334 ,  H04J3/02

摘要： A control system (Figs. 2, 3, 5, 6) and method in which multiple levels, or stages (128, 130, 132), of logical decisions are made by selectively feedforwarding output signals (356) from control modules (72) to the inputs of other modules (80), preferably through use of control modules (233) with selective feedforwarding circuits (239, 240) to logically combine during selected synchronous time slots (352) of a synchronous clock signal (Fig. 11) the result of a plurality of nonconcurrent input signals from a plurality of input devices (28, 30, 32, 34) to control an output device (26).

公开(公告)号：EP0711478A4

公开(公告)日：1997-03-12

申请号：EP94922586

申请日：1994-07-18

申请人： SQUARE D CO

发明人： BURKE GEORGE EDMUND JR ,  HORNE GEORGE MARSHALL ,  CARTER MICHAEL BARON

IPC分类号： H04L5/22 ,  G05B19/042 ,  G05B19/07 ,  G08C15/06 ,  H04J3/02 ,  H04Q9/00 ,  H04J3/04

CPC分类号： G08C15/06 ,  G05B19/0423 ,  G05B19/07 ,  G05B2219/21037 ,  G05B2219/25051 ,  G05B2219/25315 ,  G05B2219/25321 ,  G05B2219/25324 ,  G05B2219/25333 ,  G05B2219/25334 ,  H04J3/02

摘要： A control system (Figs. 2, 3, 5, 6) and method in which multiple levels, or stages (128, 130, 132), of logical decisions are made by selectively feedforwarding output signals (356) from control modules (72) to the inputs of other modules (80), preferably through use of control modules (233) with selective feedforwarding circuits (239, 240) to logically combine during selected synchronous time slots (352) of a synchronous clock signal (Fig. 11) the result of a plurality of nonconcurrent input signals from a plurality of input devices (28, 30, 32, 34) to control an output device (26).

公开(公告)号：EP0728348A1

公开(公告)日：1996-08-28

申请号：EP95933918.0

申请日：1995-09-12

申请人： SQUARE D COMPANY

发明人： RILEY, Robert, E.

IPC分类号： G08C15 ,  G05B19 ,  G06F3 ,  H03K19 ,  H04J3 ,  H04L12 ,  H04L25

CPC分类号： H04L12/40026 ,  G05B19/042 ,  G05B19/0425 ,  G05B2219/21037 ,  G05B2219/21119 ,  G05B2219/21138 ,  G05B2219/25135 ,  G05B2219/25172 ,  G05B2219/25428 ,  G05B2219/25478 ,  G05B2219/37582 ,  G08C15/12 ,  H04J3/0685 ,  H04J3/14 ,  H04L12/10 ,  H04L12/40 ,  H04L12/403 ,  H04L12/4035 ,  H04L2012/4026 ,  Y10T307/839

摘要： A programmable data link module (32) for use in a time division multiplexing control system (30) having a plurality of modules interconnected by a bus (40) for passing control signals between data link modules on a serial multiplex basis. Each module includes an integrated circuit (80) having signal conditioning circuits (180, 186 and 188) including a programmable hysteresis circuit (126), a power on reset delay circuit (190), a safety input inhibit circuit (220), a clock loss detect circuit (240), a safety output protection cicuit (262), a data verifier (260), a polarity selector for a third output terminal (350), an input synchronizer (182 and 184), a combined mode/sync output terminal (110), a multiplex clock output terminal (108), a programming circuit (232) for accepting programming over the clock bus (44) and data bus (46), input/output word extender circuits (104, 106), a high voltage protection circuit (420) including a transistor (600) and a data bus integrity checker (630).

公开(公告)号：EP0711478A1

公开(公告)日：1996-05-15

申请号：EP94922586.0

申请日：1994-07-18

申请人： SQUARE D COMPANY

发明人： BURKE, George, Edmund, Jr. ,  HORNE, George, Marshall ,  CARTER, Michael, Baron

IPC分类号： H04L5 ,  G05B19 ,  G08C15 ,  H04J3 ,  H04Q9

CPC分类号： G08C15/06 ,  G05B19/0423 ,  G05B19/07 ,  G05B2219/21037 ,  G05B2219/25051 ,  G05B2219/25315 ,  G05B2219/25321 ,  G05B2219/25324 ,  G05B2219/25333 ,  G05B2219/25334 ,  H04J3/02

摘要： A control system (Figs. 2, 3, 5, 6) and method in which multiple levels, or stages (128, 130, 132), of logical decisions are made by selectively feedforwarding output signals (356) from control modules (72) to the inputs of other modules (80), preferably through use of control modules (233) with selective feedforwarding circuits (239, 240) to logically combine during selected synchronous time slots (352) of a synchronous clock signal (Fig. 11) the result of a plurality of nonconcurrent input signals from a plurality of input devices (28, 30, 32, 34) to control an output device (26).

公开(公告)号：EP0366468A3

公开(公告)日：1991-07-31

申请号：EP89311063.5

申请日：1989-10-26

申请人： XEROX CORPORATION

发明人： Minnerd, Timothy M.

IPC分类号： G06F13/40 ,  G08C15/12

CPC分类号： G05B19/0425 ,  G05B2219/21037 ,  G05B2219/21038 ,  G05B2219/21076 ,  G05B2219/21156 ,  G05B2219/21162 ,  G05B2219/21168 ,  G05B2219/21169 ,  G05B2219/24054 ,  G05B2219/24117 ,  G05B2219/24132 ,  G05B2219/25133 ,  G05B2219/25315 ,  G05B2219/25324 ,  G08C15/12 ,  H04L7/06 ,  H04L7/08

摘要： An interface connector system includes a signal bus (18) connected to a control (12, 14) and, via a plurality of interface and connector devices (20), to load components for conveying signals between the control and the load components. Each of the interface and connector devices including address recognition circuitry (36) as well as programmable configuration selection logic (40, 44) to adapt the electrical configuration of the device to respond to a variety of load components. In addition, the signal bus and connector devices are adapted to recognize and convey various levels of signals, for example, different voltage levels representing control information, framing signals, and diagnostic command signals.

公开(公告)号：EP0309302A3

公开(公告)日：1990-09-26

申请号：EP88401830.0

申请日：1988-07-13

申请人： AUTOMATED PROCESS CONTROL, INC.

发明人： Riley, Robert E., Jr.

IPC分类号： G08C15/12 ,  H02P7/00 ,  B60R16/02

CPC分类号： G05B19/07 ,  G05B19/042 ,  G05B2219/21037 ,  G05B2219/21038 ,  G05B2219/24061 ,  G05B2219/25051 ,  G05B2219/25314 ,  G05B2219/25315 ,  G05B2219/25324 ,  G05B2219/25333 ,  G08C15/12 ,  H04L7/0008

摘要： A system for remotely controlling electrical devices includes a plurality of identical modules which can be made as multiple copies of an integrated circuit chip. Each chip includes logic for recognizing a code, the logic being programmable by EEPROMS so that each chip can be set to recognize and produce a unique address code. The modules can be connected to input or output devices, or both. All modules are intercon­nected by no more than four wires. A clock pulse source is connected to the system, the source being periodically interrupted to synchronize the system when the clock pulses restart.

公开(公告)号：EP0366468A2

公开(公告)日：1990-05-02

申请号：EP89311063.5

申请日：1989-10-26

申请人： XEROX CORPORATION

发明人： Minnerd, Timothy M.

IPC分类号： G06F13/40 ,  G08C15/12

CPC分类号： G05B19/0425 ,  G05B2219/21037 ,  G05B2219/21038 ,  G05B2219/21076 ,  G05B2219/21156 ,  G05B2219/21162 ,  G05B2219/21168 ,  G05B2219/21169 ,  G05B2219/24054 ,  G05B2219/24117 ,  G05B2219/24132 ,  G05B2219/25133 ,  G05B2219/25315 ,  G05B2219/25324 ,  G08C15/12 ,  H04L7/06 ,  H04L7/08

摘要： An interface connector system includes a signal bus (18) connected to a control (12, 14) and, via a plurality of interface and connector devices (20), to load components for conveying signals between the control and the load components. Each of the interface and connector devices including address recognition circuitry (36) as well as programmable configuration selection logic (40, 44) to adapt the electrical configuration of the device to respond to a variety of load components. In addition, the signal bus and connector devices are adapted to recognize and convey various levels of signals, for example, different voltage levels representing control information, framing signals, and diagnostic command signals.

摘要翻译： 接口连接器系统包括连接到控制器（12,14）和经由多个接口和连接器装置（20）的信号总线（18），以加载用于在控制和负载部件之间输送信号的部件。 每个接口和连接器设备包括地址识别电路（36）以及可编程配置选择逻辑（40,44），以使设备的电气配置适应各种负载组件。 此外，信号总线和连接器装置适于识别和传送各种级别的信号，例如表示控制信息，成帧信号和诊断命令信号的不同电压电平。

公开(公告)号：EP0728348B1

公开(公告)日：2003-06-11

申请号：EP95933918.5

申请日：1995-09-12

申请人： SQUARE D COMPANY

发明人： RILEY, Robert, E.

IPC分类号： G08C15/12

CPC分类号： H04L12/40026 ,  G05B19/042 ,  G05B19/0425 ,  G05B2219/21037 ,  G05B2219/21119 ,  G05B2219/21138 ,  G05B2219/25135 ,  G05B2219/25172 ,  G05B2219/25428 ,  G05B2219/25478 ,  G05B2219/37582 ,  G08C15/12 ,  H04J3/0685 ,  H04J3/14 ,  H04L12/10 ,  H04L12/40 ,  H04L12/403 ,  H04L12/4035 ,  H04L2012/4026 ,  Y10T307/839

摘要： A programmable data link module (32) for use in a time division multiplexing control system (30) having a plurality of modules interconnected by a bus (40) for passing control signals between data link modules on a serial multiplex basis. Each module includes an integrated circuit (80) having signal conditioning circuits (180, 186 and 188) including a programmable hysteresis circuit (126), a power on reset delay circuit (190), a safety input inhibit circuit (220), a clock loss detect circuit (240), a safety output protection cicuit (262), a data verifier (260), a polarity selector for a third output terminal (350), an input synchronizer (182 and 184), a combined mode/sync output terminal (110), a multiplex clock output terminal (108), a programming circuit (232) for accepting programming over the clock bus (44) and data bus (46), input/output word extender circuits (104, 106), a high voltage protection circuit (420) including a transistor (600) and a data bus integrity checker (630).

公开(公告)号：EP0876715A1

公开(公告)日：1998-11-11

申请号：EP97904075.0

申请日：1997-02-05

申请人： LUTRON ELECTRONICS CO., INC.

发明人： MOSEBROOK, Donald, R. ,  HOUGGY, David, E. ,  PALMER, Robert, G., Jr. ,  SPIRA, Joel, S. ,  HAUSMAN, Donald, F., Jr. ,  MOSELEY, Robin, C. ,  LUCHACO, David, G.

IPC分类号： G05B19 ,  G08C17 ,  G08C19 ,  H02J13 ,  H04B3 ,  H04B7 ,  H04N5 ,  H04Q9 ,  H05B37

CPC分类号： G05B19/0423 ,  G05B2219/21037 ,  G05B2219/21042 ,  G05B2219/24102 ,  G05B2219/25181 ,  G05B2219/25188 ,  G05B2219/25196 ,  G05B2219/25209 ,  G05B2219/25427 ,  G05B2219/25448 ,  G05B2219/2642 ,  H02J13/0075 ,  H05B37/0263 ,  H05B37/0272 ,  Y02B70/3241 ,  Y04S20/227 ,  Y10T307/406 ,  Y10T307/477

摘要： Apparatus for controlling at least one electrical device (54) by remote control includes at least one control device (50) coupled to the electrical device (54) by a power line connection, the control device (50) having a switch (58, 59) for adjusting the status of the electrical device (54). The control device (50) has a radio frequency (RF) transmitter/receiver for adjusting and communicating the status of the electrical device. A master control unit (20) is provided having at least one actuator and status indicator (22). The master unit (20) has a transmitter/receiver for transmitting RF information to control the status of the electrical device and for receiving the status information from the control device (50). The master control unit (20) indicates status of the electrical device(54). A repeater transmitter/receiver (40) is provided for receiving the RF signal from the master unit (20) and transmitting control information to the control device (50) and for receiving the status information.