公开(公告)号：EP2810282A4

公开(公告)日：2016-02-17

申请号：EP13743013

申请日：2013-02-01

申请人： EMPIRIX INC

发明人： EIDELMAN SERGEY

IPC分类号： G11C29/56 ,  G01R31/317 ,  G06F9/445 ,  G06F11/22 ,  G06F21/00

CPC分类号： G06F11/2268 ,  G06F9/44505 ,  G06F21/00

公开(公告)号：EP1215578A3

公开(公告)日：2009-10-21

申请号：EP01124624.6

申请日：2001-10-15

申请人： MICROSOFT CORPORATION

发明人： Vachon, Andre F.

IPC分类号： G06F11/22 ,  G06F11/14

CPC分类号： G06F11/0778 ,  G06F11/0715 ,  G06F11/1415 ,  G06F11/2268

摘要： A system and method is provided for generating a summary dump file from a system or application crash dump or core dump file without the need for referencing a large symbol table file. A crash dump file with a referencing portion containing references to certain pertinent information ( e.g. , data structures) including references conventionally not found in crash dump files. The data structures referenced in the referencing portion have been found to be optimal for analyzing faults residing in a crash dump file. The crash dump file may be a complete crash dump file of an operating system or a kernel memory dump. Alternatively, the crash dump file may be a crash dump file of an application program. A stand alone extraction tool is also provided for extracting pertinent information from the crash dump or core dump file by utilizing information in the referencing portion. The stand alone tool generates a summary or mini dump file of the crash dump file.

摘要翻译： 提供了一种系统和方法，用于从系统或应用程序崩溃转储或核心转储文件生成摘要转储文件，而无需引用大型符号表文件。 具有引用部分的故障转储文件，其包含对包含通常在故障转储文件中未找到的引用的某些相关信息（例如，数据结构）的引用。 已经发现引用部分中引用的数据结构对于分析故障转储文件中存在的故障是最佳的。 崩溃转储文件可能是操作系统或内核内存转储的完整崩溃转储文件。 或者，崩溃转储文件可能是应用程序的崩溃转储文件。 还提供了独立提取工具，用于通过利用参考部分中的信息从故障转储或核心转储文件中提取相关信息。 独立工具会生成崩溃转储文件的摘要或小型转储文件。

公开(公告)号：EP1237088A3

公开(公告)日：2006-05-31

申请号：EP01117566.8

申请日：2001-07-20

申请人： Hitachi, Ltd.

发明人： Kawaguchi, Masahiro ,  Yokohata, Shizuo ,  Nakayama, Shinichi ,  Goto, Youichi

IPC分类号： G06F11/34 ,  G06F11/22

CPC分类号： G06F11/348 ,  G06F11/2268 ,  G06F11/349

摘要： A storage system includes a storage controller (20) connected to higher-level devices (40, 30, 10) and a plurality of storages (50-53) connected to the storage controller for storing data from the higher-level devices. The storage controller (20) includes a channel controller (21) for establishing interface for the higher-level devices, the channel controller including trace information representing details of the interface, and storages (23, 50-53) for storing the trace information from the channel controller in a format which can be accessed by the higher-level devices. In this configuration, when the channel controller receives a trace information fetching indication from one of the higher-level devices, the channel controller transfers trace information to a cache memory (23) and the storages (50-53) or to the cache memory or the storages.

公开(公告)号：EP1254402B1

公开(公告)日：2003-10-08

申请号：EP00973998.8

申请日：2000-10-27

申请人： General Electric Company

发明人： VARMA, Anil ,  RODDY, Nicholas, Edward ,  GIBSON, David, Richard

IPC分类号： G05B23/02

CPC分类号： G05B23/0281 ,  B61C17/04 ,  B61C17/12 ,  G06F11/2257 ,  G06F11/2268 ,  Y02T30/10

摘要： The present invention discloses system and method for analyzing continuous parameter data from a malfunctioning locomotive or other large land-based, self-powered transport equipment. The method allows for receiving new continuous parameter data (232) comprising a plurality of anomaly definitions from the malfunctioning equipment. The method further allows for selecting a plurality of distinct anomaly definitions (233) from the new continuous parameter data. Respective generating steps allow for generating at least one distinct anomaly definition cluster (236) from the plurality of distinct anomaly definitions and for generating a plurality of weighted repair and distinct anomaly definition cluster combinations. An identifying step allows for identifying at least one repair (238) for the at least one distinct anomaly definition cluster using the plurality of weighted repair and distinct anomaly definition cluster combinations.

公开(公告)号：EP1026590A3

公开(公告)日：2002-10-09

申请号：EP00300360.5

申请日：2000-01-19

申请人： LUCENT TECHNOLOGIES INC.

发明人： Daudelin, Douglas S. ,  McNerney, Frank J. ,  Wells, Richard P.

IPC分类号： G06F11/22 ,  G01R31/3177

CPC分类号： G06F11/2268 ,  G06F11/0757

摘要： A circuit pack self-testing system adapted to carry out tests on circuit pack electronic devices is disclosed. The self-testing system executes various test programs in a test suite, and keeps an historical record of test results from previous test suites in non-volatile memory. The historical record is updated only when the most recent results are different than the last-recorded results, and are easily accessible for circuit pack failure analysis and repair. At the beginning of each test suite, a temporary record for containing test results is initialized. As the system progresses through the various test programs, the test programs update the temporary record with test results. In preferred embodiment, this temporary record is created by utilizing two registers, a start register and an end register. The start register stores the beginning of each test program (test portion) in a test suite and the end register stores the ending of each test program. If a test suite runs to completion the start and end registers will contain the same value. However, if a test program in a test suite cannot run to completion, the value stored in the start register will be one greater than the value stored in the end register. Should a fault, possibly intermittent, on the circuit pack under test cause a test program to halt or hang, a sanity-recovery mechanism causes the self-testing system to be restarted. Prior to initializing the temporary record at the beginning of the next test suite, the temporary record is examined to determine whether a previously executed test suite failed to run to completion. If the examination shows that it failed to run to completion, and the failure information is different than the last-recorded results in the historical record, then information from the temporary record indicating this failure is stored in the historical record.

公开(公告)号：EP0516126A1

公开(公告)日：1992-12-02

申请号：EP92109059.3

申请日：1992-05-29

申请人： Bull HN Information Systems Inc.

发明人： Edwards,David S. ,  Shelly,William A. ,  Chang,Jiuyih ,  Inoshita,Minoru ,  Trubisky,Leonard G.

IPC分类号： G06F11/00 ,  G06F11/14 ,  G06F12/08

CPC分类号： G06F12/0817 ,  G06F11/1044 ,  G06F11/1064 ,  G06F11/1402 ,  G06F11/1405 ,  G06F11/2268

摘要： A fault tolerant computer system includes at least two central processing units each having a cache memory and a parity error detector adapted to sense parity errors in blocks of information read from and write to cache and to issue a cache parity read or write error flag if a parity error is sensed. A system bus couples the CPU to a System Control Unit having a parity error correction facility, and a memory bus couples the SCU to a main memory. An error recovery control feature distributed across the CPU, a Service Processor and the operating system software is responsive to the sensing of a read parity error flag in a sending CPU and a write parity error flag in a receiving CPU in conjunction with a siphon operation for transferring the faulting block from the sending CPU to main memory via the SCU (in which given faulting block is corrected) and for subsequently transferring the corrected memory block from main memory to the receiving CPU when a retry is instituted.

摘要翻译： 容错计算机系统包括至少两个中央处理单元，每个中央处理单元具有高速缓冲存储器和奇偶校验错误检测器，该奇偶校验错误检测器适于检测从高速缓冲存储器读取和写入高速缓存的信息块中的奇偶校验错误，并发出高速缓存奇偶校验读或写错误标志，如果 奇偶校验错误被检测。 系统总线将CPU耦合到具有奇偶纠错设施的系统控制单元，并且存储器总线将SCU耦合到主存储器。 分布在CPU，服务处理器和操作系统软件上的错误恢复控制功能响应于在发送CPU中读取奇偶校验错误标志和接收CPU中的写奇偶校验错误标志的检测，结合虹吸操作 通过SCU（其中给定故障块被校正）将故障块从发送CPU传送到主存储器，并且用于随后在重试时将校正的存储器块从主存储器传送到接收CPU。

公开(公告)号：EP0087314B1

公开(公告)日：1989-04-19

申请号：EP83300907.9

申请日：1983-02-22

申请人： FUJITSU LIMITED

发明人： Shioya, Katsuhiko c/o Fujitsu Ltd. Patent Dpt. ,  Ifuku, Tetsuhiko c/o Fujitsu Ltd. Patent Dpt. ,  Inamasu, Seiichi c/o Fujitsu Ltd. Patent Dpt.

IPC分类号： G06F11/26

CPC分类号： G06F11/2236 ,  G06F11/2268 ,  G06F11/273

摘要： In a logical unit provided with a plurality of internal registers (12 to 15; 20), an internal memory (11-1, 11-2; 21) and a combinational circuit (16), such as an arithmetic unit, at least one (13 or 14; 20) of the plurality of internal registers is arranged to be scanned in and out. During diagnosis, when executing an instruction which makes reference to the internal memory (11-1, 11-2; 21), the register than can be scanned in and scanned out is used in place of the internal memory 11-1, 11-2; 21) for diagnosing the combinational circuit (16).

公开(公告)号：EP0141744A3

公开(公告)日：1988-03-16

申请号：EP84402193

申请日：1984-10-31

申请人： DIGITAL EQUIPMENT CORPORATION

发明人： Fossum, Tryggve ,  Shively, Milton L.

IPC分类号： G06F11/26

CPC分类号： G06F11/2273 ,  G06F7/00 ,  G06F7/483 ,  G06F11/16 ,  G06F11/2242 ,  G06F11/2268

摘要： A mechanism for continually testing a floating point accelerator processor (FPAP) element or other processor element in a suitable multiprocessor system. At least two processors, such as an instruction execution processor(EU) and a FPAP, are connected to a common input bus to concurrently receive the same information (opcodes and operands). Both the EU and the FPAP decode the opcodes. When the FPAP decodes an opcode for an operation to be performed by the EU, the FPAP, instead of remaining idle while the EU operates, executes a diagnostic operation. The FPAP selects the particular diagnostic operation to perform in each instance from among a multiplicity of available diagnostic operations. The selection of a diagnostic operation is dependent on the instruction to be executed by the EU; in order to not slow down the overall execution rate of the system, a diagnostic operation is chosen whose execution time is matched to the execution time of the instruction being performed by the EU; that is, a diagnostic operation is selected such that the FPAP will finish the operation before the EU will finish executing its instruction. Operand data supplied to the EU on the input bus is used by the diagnostic operations, to add a degree of randomness to the test signals and permit detection of bits forced to a steady value of zero or one. For some diagnostic operations, one or more variables may be obtained from general purpose registers.

公开(公告)号：EP2405355A2

公开(公告)日：2012-01-11

申请号：EP11167159.0

申请日：2011-05-23

申请人： FUJITSU LIMITED

发明人： Sano, Koji

IPC分类号： G06F11/22

CPC分类号： G06F11/2268

摘要： An information processing system that processes received commands and data, the information processing system includes: an internal circuit that processes the received commands and data; a memory that stores the received commands and data as history; and a control circuit that reads the commands and data in the memory and outputs read commands and data to the internal circuit, in response to detection of a failure in the internal circuit.

摘要翻译： 一种处理接收到的命令和数据的信息处理系统，所述信息处理系统包括：处理所接收的命令和数据的内部电路; 将所接收的命令和数据存储为历史的存储器; 以及控制电路，其响应于检测到内部电路中的故障，读取存储器中的命令和数据并将读取命令和数据输出到内部电路。

公开(公告)号：EP0974847B1

公开(公告)日：2003-06-04

申请号：EP99113053.5

申请日：1999-07-01

申请人： Infineon Technologies AG

发明人： Krasser, Hans-Jürgen ,  Schamberger, Florian

IPC分类号： G01R31/3187 ,  G06F11/22 ,  G06F11/00 ,  G11C29/00

CPC分类号： G11C29/12 ,  G06F11/2268 ,  G11C29/44