公开(公告)号：EP4394616A1

公开(公告)日：2024-07-03

申请号：EP23216045.7

申请日：2023-12-12

申请人： STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

发明人： ZAMBOTTI, Paolo Sergio ,  BOESCH, Thomas ,  DESOLI, Giuseppe ,  BETZ, Wolfgang Johann ,  SIORPAES, David

IPC分类号： G06F15/78

CPC分类号： G06F15/7875 ,  G06F15/7889

摘要： A system includes a host processor, a memory, a hardware accelerator and a configuration controller. The host processor, in operation, controls execution of a multi-stage processing task. The memory, in operation, stores data and configuration information. The hardware accelerator, in operation preforms operations associated with stages of the multi-stage processing task. The configuration controller is coupled to the host processor, the hardware accelerator, and the memory. The configuration controller executes a linked list of configuration operations, for example, under control of a finite state machine. The linked list consists of configuration operations selected from a defined set of configuration operations. Executing the linked list of configuration operations configures the plurality of configuration registers of the hardware accelerator to control operations of the hardware accelerator associated with a stage of the multi-stage processing task. The configuration controller may retrieve the linked list from the memory via a high-speed data bus.

公开(公告)号：EP3710948B1

公开(公告)日：2024-05-01

申请号：EP18755952.1

申请日：2018-07-13

IPC分类号： G06F30/34 ,  G06F9/48 ,  G06F9/50 ,  G06F15/76 ,  G06F15/78 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17756 ,  H03K19/1776

CPC分类号： G06F15/76 ,  G06F15/7871 ,  G06F15/7875 ,  G06F9/4843 ,  G06F9/5011 ,  G06F9/5077 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/1776 ,  H03K19/17756 ,  G06F30/34 ,  G06F30/30