-
公开(公告)号：EP3531348A1
公开(公告)日：2019-08-28
申请号：EP19159082.7
申请日：2019-02-25
摘要： Embodiments of a device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit, and an arithmetic unit (700) coupled to the reconfigurable stream switch. The arithmetic unit (700) has a plurality of inputs and at least one output, and the arithmetic unit (700) is solely dedicated to performance of a plurality of parallel operations. Each one of the plurality of parallel operations carries out a portion of the formula: output = AX + BY + C.
-
2.发明公开
公开(公告)号：EP4394615A1
公开(公告)日：2024-07-03
申请号：EP23216064.8
申请日：2023-12-12
发明人： GIRARDI, Francesca , DESOLI, Giuseppe , SUSELLA, Ruggero , BOESCH, Thomas , ZAMBOTTI, Paolo Sergio
IPC分类号： G06F15/173 , G06F15/82
CPC分类号： G06F15/82 , G06F15/17331
摘要： A hardware accelerator (120) includes functional circuits (124, 126) and streaming engines (128). An interface (170) is coupled to the plurality of streaming engines (128). The interface (170), in operation, performs stream cipher operations on data words associated with data streaming requests. The performing of a stream cipher operation on a data word includes generating a mask based on an encryption ID associated with a streaming engine of the plurality of streaming engines (128) and an address associated with the data word, and XORing the generated mask with the data word. The hardware accelerator (120) may include configuration registers (170) to store configuration information indicating a respective security state associated with functional circuits (124, 126) and streaming engines (128) of the hardware accelerator (120), which may be used to control performance of operations by the hardware accelerator (120).
-
公开(公告)号：EP3944156A1
公开(公告)日：2022-01-26
申请号：EP21178343.6
申请日：2021-06-08
摘要： Techniques and systems are provided for implementing a convolutional neural network. One or more convolution accelerators (600) are provided that each include a feature line buffer memory, a kernel buffer memory, and a plurality of multiply-accumulate, MAC circuits arranged to multiply and accumulate data. In a first operational mode the convolutional accelerator (600) stores feature data in the feature line buffer memory and stores kernel data in the kernel data buffer memory. In a second mode of operation, the convolutional accelerator (600) stores kernel decompression tables in the feature line buffer memory.
-
公开(公告)号：EP3859535A1
公开(公告)日：2021-08-04
申请号：EP21153708.9
申请日：2021-01-27
IPC分类号： G06F12/02 , G11C11/22 , G11C11/408 , G11C11/4093 , G11C11/419 , G11C7/10 , G11C8/04 , G11C8/08 , G11C8/10 , G11C11/54 , G06N3/04 , G06N3/063
摘要： A system includes a random access memory organized into indivudally addressable words. Streaming access control circuitry is coupled to word lines of the random access memory. The streaming access control circuitry responds to a request to access a plurality of individually addressable words of a determined region of the random access memory by generating control signals to drive the word lines to streamingly access the plurality of individually addressable words of the determined region. The request indicates an offset associated with the determined region and a pattern associated with the streaming access.
-
公开(公告)号：EP3798853A2
公开(公告)日：2021-03-31
申请号：EP20194994.8
申请日：2020-09-08
发明人： CHAWLA, Nitin , DESOLI, Giuseppe , GROVER, Anuj , BOESCH, Thomas , SINGH, Surinder Pal , AYODHYAWASI, Manuj
摘要： A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.
-
公开(公告)号：EP3836144A1
公开(公告)日：2021-06-16
申请号：EP20212102.6
申请日：2020-12-07
发明人： CHAWLA, Nitin , GROVER, Anuj , DESOLI, Giuseppe , DHORI, Kedar Janardan , BOESCH, Thomas , KUMAR, Promod
IPC分类号： G11C11/417 , G11C5/14
摘要： Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.
-
公开(公告)号：EP3798853A3
公开(公告)日：2021-06-16
申请号：EP20194994.8
申请日：2020-09-08
发明人： CHAWLA, Nitin , DESOLI, Giuseppe , GROVER, Anuj , BOESCH, Thomas , SINGH, Surinder Pal , AYODHYAWASI, Manuj
摘要： A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.
-
公开(公告)号：EP3531348A8
公开(公告)日：2020-05-06
申请号：EP19159082.7
申请日：2019-02-25
摘要： Embodiments of a device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit, and an arithmetic unit (700) coupled to the reconfigurable stream switch. The arithmetic unit (700) has a plurality of inputs and at least one output, and the arithmetic unit (700) is solely dedicated to performance of a plurality of parallel operations. Each one of the plurality of parallel operations carries out a portion of the formula: output = AX + BY + C.
-
公开(公告)号：EP3531349A1
公开(公告)日：2019-08-28
申请号：EP19159070.2
申请日：2019-02-25
摘要： Embodiments of a device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and an arithmetic unit (810) coupled to the reconfigurable stream switch. The arithmetic unit (810) has at least one input and at least one output. The at least one input is arranged to receive streaming data passed through the reconfigurable stream switch, and the at least one output is arranged to stream resultant data through the reconfigurable stream switch. The arithmetic unit (810) also has a plurality of data paths. At least one of the plurality of data paths is solely dedicated to performance of operations that accelerate an activation function represented in the form of a piece-wise second order polynomial approximation.
-
公开(公告)号：EP4394616A1
公开(公告)日：2024-07-03
申请号：EP23216045.7
申请日：2023-12-12
发明人： ZAMBOTTI, Paolo Sergio , BOESCH, Thomas , DESOLI, Giuseppe , BETZ, Wolfgang Johann , SIORPAES, David
IPC分类号： G06F15/78
CPC分类号： G06F15/7875 , G06F15/7889
摘要： A system includes a host processor, a memory, a hardware accelerator and a configuration controller. The host processor, in operation, controls execution of a multi-stage processing task. The memory, in operation, stores data and configuration information. The hardware accelerator, in operation preforms operations associated with stages of the multi-stage processing task. The configuration controller is coupled to the host processor, the hardware accelerator, and the memory. The configuration controller executes a linked list of configuration operations, for example, under control of a finite state machine. The linked list consists of configuration operations selected from a defined set of configuration operations. Executing the linked list of configuration operations configures the plurality of configuration registers of the hardware accelerator to control operations of the hardware accelerator associated with a stage of the multi-stage processing task. The configuration controller may retrieve the linked list from the memory via a high-speed data bus.
-
-
-
-
-
-
-
-
-
搜索结果
19 条记录 (耗时 0.016 秒)
