公开(公告)号：EP1054401B1

公开(公告)日：2004-03-03

申请号：EP00303986.4

申请日：2000-05-11

Applicant: Texas Instruments Incorporated

Inventor： Leung, Michael ,  Fu, Leo

IPC: G11B20/10 ,  G11B20/18

CPC classification number: G11B20/10064 ,  G11B20/10009 ,  G11B20/10074 ,  G11B20/1833

公开(公告)号：EP0777211B1

公开(公告)日：2002-04-03

申请号：EP96119296.0

申请日：1996-12-02

Applicant: CIRRUS LOGIC, INC.

Inventor： Reed, David E. ,  Bliss, William G.

IPC: G11B5/02 ,  G11B5/09 ,  G11B20/10 ,  G11B20/14 ,  G11B20/08

CPC classification number: H04L7/0029 ,  G11B5/09 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10055 ,  G11B20/10064 ,  G11B20/10074 ,  G11B20/1258 ,  G11B20/1403 ,  G11B2020/10888 ,  G11B2020/1234 ,  G11B2020/1282 ,  H04L7/0004 ,  H04L7/0062 ,  H04L2007/047

Abstract: A sampled amplitude read channel reads user data and embedded servo data stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values. A write frequency synthesizer generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, a read frequency synthesizer generates a fixed sampling clock at a frequency slightly higher than the write frequency at the outer zone. A sampling device samples the analog read signal at this fixed sampling rate across the data zones and servo wedges to generate a sequence of discrete time channel samples that are not synchronized to the baud rate. Before sampling, an analog receive filter processes the read signal to attenuate aliasing noise without having to adjust its spectrum across data zones or servo wedges. A discrete time equalizing filter equalizes the channel samples according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval tau and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a synchronous data clock for clocking a discrete time sequence detector and pulse detector which detect the digital user and servo data from the interpolated sample values.

公开(公告)号：EP1054401A2

公开(公告)日：2000-11-22

申请号：EP00303986.4

申请日：2000-05-11

Applicant: Texas Instruments Incorporated

Inventor： Leung, Michael ,  Fu, Leo

IPC: G11B20/10 ,  G11B20/18

CPC classification number: G11B20/10064 ,  G11B20/10009 ,  G11B20/10074 ,  G11B20/1833

Abstract: Device and method of EEPR4 post processing in an EPR4 detection system to remove single bit errors by applying 1+D to the samples and comparing this to (1-D)(1+D) 3 to the detected EPR4 bits.

Abstract translation: 在EPR4检测系统中进行EEPR4后处理的装置和方法，通过对样本应用1 + D并将其与（1-D）（1 + D）<3>进行比较，以检测EPR4位。

公开(公告)号：EP1271479A3

公开(公告)日：2006-12-06

申请号：EP02253884.7

申请日：2002-05-31

Applicant: STMicroelectronics, Inc.

Inventor： Heydari, Fereidoon ,  Ozdemir, Hakan

IPC: G11B27/30

CPC classification number: G11B20/10009 ,  G11B5/59633 ,  G11B20/10055 ,  G11B20/10074 ,  G11B20/10296 ,  G11B20/1217 ,  G11B20/1496 ,  G11B27/3027 ,  G11B2020/1484 ,  G11B2220/2516 ,  H03M7/16

Abstract: A new technique incorporates a 1/4-rate Hard Disk Drive (HDD) servo-data encoding into a Partial Response Maximum Likelihood (PRML) read channel. The limitation of the HDD servo-track writer is the maximum frequency associated with writing the servo data while maintaining a level of data alignment between the data in the adjacent tracks (coherency). The 1/4 code allows the servo data to be written at the maximum coherency bandwidth. Specifically, the data is read back (or sampled) at twice the write frequency. This increases the data redundancy while also increasing the data density and the disk storage capacity. The 1/4 coding can also be applied to conventional HDD dibit coding. Specifically, the 1/4-coding scheme reads each dibit-coded servo-data transition 01 as 0011, and reads each non-transition 00 (or 0) as 0000. The 1/4 coding and its matched Viterbi detector can also increase the data detection in comparison to conventional peak-detection schemes. And although the 1/4 coding scheme is described in conjunction with a PR4-type servo channel, it can also be used with an EPR4-type servo channel and other types of servo channels.

公开(公告)号：EP1271479A2

公开(公告)日：2003-01-02

申请号：EP02253884.7

申请日：2002-05-31

Applicant: STMicroelectronics, Inc.

Inventor： Heydari, Fereidoon ,  Ozdemir, Hakan

IPC: G11B5/596

CPC classification number: G11B20/10009 ,  G11B5/59633 ,  G11B20/10055 ,  G11B20/10074 ,  G11B20/10296 ,  G11B20/1217 ,  G11B20/1496 ,  G11B27/3027 ,  G11B2020/1484 ,  G11B2220/2516 ,  H03M7/16

Abstract: A new technique incorporates a 1/4-rate Hard Disk Drive (HDD) servo-data encoding into a Partial Response Maximum Likelihood (PRML) read channel. The limitation of the HDD servo-track writer is the maximum frequency associated with writing the servo data while maintaining a level of data alignment between the data in the adjacent tracks (coherency). The 1/4 code allows the servo data to be written at the maximum coherency bandwidth. Specifically, the data is read back (or sampled) at twice the write frequency. This increases the data redundancy while also increasing the data density and the disk storage capacity. The 1/4 coding can also be applied to conventional HDD dibit coding. Specifically, the 1/4-coding scheme reads each dibit-coded servo-data transition 01 as 0011, and reads each non-transition 00 (or 0) as 0000. The 1/4 coding and its matched Viterbi detector can also increase the data detection in comparison to conventional peak-detection schemes. And although the 1/4 coding scheme is described in conjunction with a PR4-type servo channel, it can also be used with an EPR4-type servo channel and other types of servo channels.

Abstract translation: 一种新技术将1/4速度硬盘驱动器（HDD）伺服数据编码结合到部分响应最大似然（PRML）读通道中。 HDD伺服磁道写入器的限制是与伺服数据写入相关联的最大频率，同时保持相邻轨道中的数据之间的数据对齐水平（相干性）。 1/4代码允许以最大相干带宽写入伺服数据。 具体来说，以写入频率的两倍读取（或采样）数据。 这增加了数据冗余，同时也增加了数据密度和磁盘存储容量。 1/4编码也可以应用于常规HDD双位编码。 具体地说，1/4编码方式将每个二进制编码的伺服数据转换01读为0011，并将每个非转换00（或0）读取为0000. 1/4编码及其匹配维特比检测器也可以增加 数据检测与传统的峰值检测方案相比。 虽然1/4编码方案与PR4型伺服信道一起描述，但也可以与EPR4型伺服信道和其他类型的伺服信道一起使用。

公开(公告)号：EP0777211A2

公开(公告)日：1997-06-04

申请号：EP96119296.0

申请日：1996-12-02

Applicant: CIRRUS LOGIC, INC.

Inventor： Reed, David E. ,  Bliss, William G.

IPC: G11B5/02 ,  G11B5/09 ,  G11B20/08 ,  G11B20/14

CPC classification number: H04L7/0029 ,  G11B5/09 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10055 ,  G11B20/10064 ,  G11B20/10074 ,  G11B20/1258 ,  G11B20/1403 ,  G11B2020/10888 ,  G11B2020/1234 ,  G11B2020/1282 ,  H04L7/0004 ,  H04L7/0062 ,  H04L2007/047

Abstract: A sampled amplitude read channel reads user data and embedded servo data stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values. A write frequency synthesizer generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, a read frequency synthesizer generates a fixed sampling clock at a frequency slightly higher than the write frequency at the outer zone. A sampling device samples the analog read signal at this fixed sampling rate across the data zones and servo wedges to generate a sequence of discrete time channel samples that are not synchronized to the baud rate. Before sampling, an analog receive filter processes the read signal to attenuate aliasing noise without having to adjust its spectrum across data zones or servo wedges. A discrete time equalizing filter equalizes the channel samples according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval τ and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a synchronous data clock for clocking a discrete time sequence detector and pulse detector which detect the digital user and servo data from the interpolated sample values.

Abstract translation: 甲采样幅度读通道读出的用户数据以及通过从离散时间内插样本值序列检测的数字数据存储在磁介质上嵌入的伺服数据。 写频率合成基因速率的写时钟，用于以预定的波特率的数字数据写入所述磁介质用于所选择的区域，并且在重放时，读出频率合成基因率比在写频率稍高的频率的固定的采样时钟 外区。 的取样装置取样该模拟在整个数据区和伺服楔该固定取样速率读出信号，以生成离散时间信道样本序列并不同步于波特率。 采样模拟接收滤波器之前处理所述读信号以衰减混叠噪声，而无需跨数据区域或伺服楔调整其频谱。 离散时间均衡滤波器均衡信道样本gemäß到预定部分响应（PR4，EPR4，EEPR4等）。 内插的定时恢复电路，响应于均衡信道样本，计算到内插间隔tau和，并且响应于此，内插样值速率基因率基本上同步于波特。 定时恢复电路，以便基因率计时离散时间序列检测器和脉冲检测器用于检测从内插样本值的数字用户和伺服数据的同步数据时钟。

公开(公告)号：EP0751519B1

公开(公告)日：2001-08-01

申请号：EP96303435.0

申请日：1996-05-15

Applicant: QUANTUM CORPORATION

Inventor： Fitzpatrick, Kelly K.

IPC: G11B20/10 ,  H04L25/497

CPC classification number: G11B20/10074 ,  G11B20/10009 ,  H04L25/497

公开(公告)号：EP0769781A2

公开(公告)日：1997-04-23

申请号：EP96307565.0

申请日：1996-10-18

Applicant: CIRRUS LOGIC, INC.

Inventor： Spurbeck, Mark S. ,  Behrens, Richard T.

IPC: G11B20/14

CPC classification number: H04L7/0029 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10055 ,  G11B20/10064 ,  G11B20/10074 ,  G11B20/1258 ,  G11B20/1403 ,  G11B2020/1234 ,  H04L2007/047

Abstract: A sampled amplitude read channel reads information stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values, the interpolated sample values generated by interpolating a sequence of discrete time channel sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic medium. A write VFO generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, the write VFO generates a sampling clock at a frequency slightly higher than the write frequency. A sampling device samples the analog read signal at the sampling clock rate to generate a sequence of discrete time channel samples that are not synchronized to the baud rate, and the channel samples are equalized by a discrete time equalizing filter according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit (B100), responsive to the equalized channel samples, computes an interpolation interval τ and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a data clock (B104) for clocking a discrete time sequence detector (34) which detects the digital data (B102) from the interpolated sample values. In a cost reduced implementation, the interpolation filter coefficients are computed in real time as a function of the interpolation interval τ.

Abstract translation: 采样幅度读取通道通过从离散时间内插样本值序列中检测数字数据来读取存储在磁性介质上的信息，内插采样值，通过内插由模拟读取信号中的采样脉冲产生的离散时间通道采样值序列而产生 从位于磁介质上的磁读头。 写入VFO产生用于以预定波特率将数字数据写入磁性介质的写时钟用于所选择的区域，并且在读回时，写入VFO以略高于写入频率的频率产生采样时钟。 采样设备以采样时钟速率对模拟读取信号进行采样，以产生不与波特率同步的离散时间信道采样序列，并且通过离散时间均衡滤波器根据预定的部分响应（ PR4，EPR4，EEPR4等）。 内插定时恢复电路（B100）响应于均衡信道采样，计算内插间隔τ，并且响应于此产生基本上与波特率同步的内插采样值。 定时恢复电路还生成用于对从内插样本值检测数字数据（B102）的离散时间序列检测器（34）进行计时的数据时钟（B104）。 在成本降低的实现中，内插滤波器系数作为插值间隔τ的函数被实时计算。

公开(公告)号：EP0751519A2

公开(公告)日：1997-01-02

申请号：EP96303435.0

申请日：1996-05-15

Applicant: QUANTUM CORPORATION

Inventor： Fitzpatrick, Kelly K.

IPC: G11B20/10 ,  H04L25/497

CPC classification number: G11B20/10074 ,  G11B20/10009 ,  H04L25/497

Abstract: An EPR4 detector (36) comprises a PR4 Viterbi detector (38) and an EPR4 post-processor (40) for improving estimated output sequence at an output of the PR4 Viterbi detector (38). The PR4 Viterbi detector (38) produces digital estimates of coded digital information values into the channel in accordance with a path through a PR4 trellis and produces other path information relating to other paths through the PR4 trellis. The EPR4 post-processor (40) has a PR4 path storage circuit for receiving and storing the estimated sequence of coded digital information values which corresponds to a PR4 path through a sequence of states of an EPR4 trellis; an error-event selection circuit for receiving the other path information from the PR4 Viterbi detector for generating non-overlapping error-events from a set of error-events deviating from the PR4 path through the EPR4 trellis stored in the PR4 path storage circuit, and a path correction circuit connected to the PR4 path storage circuit and to the error-event selection circuit for correcting non-overlapping error-events deviating from the PR4 path through the EPR4 trellis, and for putting out a corrected estimated sequence of coded digital information values. An EPR4 detection method is also disclosed.

Abstract translation: 扩展部分响应类别IV（EPR4）检测器包括PR4维特比检测器，从PR4均衡采样数据检测通道接收数字样本，并产生对应于通过PR4网格的确定路径的编码数字数据的估计序列，以及其他路径 通过PR4网格与其他路径相关的信息。 后处理器连接到PR4维特比检测器和PR4均衡采样数据检测通道。 后处理器包括PR4路径存储电路，用于接收和存储经编码的数字信息值的估计序列，其通过EPR4网格指定包括状态序列的PR4路径。 错误事件选择电路从PR4维特比检测器接收另一路径信息，用于从一组错误事件中选择非重叠的错误事件。 连接到PR4路径存储电路和错误事件选择电路的路径校正电路校正通过EPR4网格偏离PR4路径的不重叠的错误事件，并且输出经修正的编码数字数据的估计序列 。

公开(公告)号：EP1054401A3

公开(公告)日：2001-09-05

申请号：EP00303986.4

申请日：2000-05-11

Applicant: Texas Instruments Incorporated

Inventor： Leung, Michael ,  Fu, Leo

IPC: G11B20/10 ,  G11B20/18

CPC classification number: G11B20/10064 ,  G11B20/10009 ,  G11B20/10074 ,  G11B20/1833

Abstract: Device and method of EEPR4 post processing in an EPR4 detection system to remove single bit errors by applying 1+D to the samples and comparing this to (1-D)(1+D) 3 to the detected EPR4 bits.