公开(公告)号：EP2985699A4

公开(公告)日：2016-05-11

申请号：EP14788484

申请日：2014-04-10

Applicant: HUAWEI TECH CO LTD

Inventor： RUAN YUAN ,  CHEN MINGYU

IPC: G06F12/08 ,  G06F13/16

CPC classification number: G11C11/40607 ,  G06F12/02 ,  G06F13/1673 ,  G11C7/1063 ,  G11C7/1072

Abstract: Embodiments of the present invention provide a memory access method and a memory system. A memory controller sends a memory access instruction, a lower-order address signal, a first chip select signal, and a first higher-order address signal to a first level buffer chip, delays a second higher-order address signal to obtain a delayed address signal, and sends the delayed address signal to a second level buffer chip. The first level buffer chip gates a target second level buffer chip according to a preset mapping relationship, the first chip select signal, and the first higher-order address signal, and sends the memory access instruction and the lower-order address signal to the target second level buffer chip. The target second level buffer chip determines a target memory module according to the delayed address signal and a second chip select signal, determines a target memory chip according to the lower-order address signal, acquires target data from the target memory chip according to the memory access instruction, and returns the target data to the memory controller. In the embodiments of the present invention, a cascading manner of a system memory is changed to a tree-like topological form. This avoids a protocol conversion problem, reduces the memory access time, and improves the memory access efficiency.

Abstract translation: 本发明的实施例提供一种存储器访问方法和存储器系统。 存储器控制器向第一级缓冲器芯片发送存储器访问指令，低阶地址信号，第一片选信号和第一高位地址信号，延迟第二高阶地址信号以获得延迟地址 信号，并将延迟的地址信号发送到第二级缓冲芯片。 第一级缓冲器芯片根据预设的映射关系，第一片选信号和第一高位地址信号对目标第二级缓冲器芯片进行门控，并将存储器访问指令和低位地址信号发送到目标 二级缓冲芯片。 目标第二级缓冲器芯片根据延迟的地址信号和第二芯片选择信号确定目标存储器模块，根据低阶地址信号确定目标存储器芯片，根据存储器从目标存储器芯片获取目标数据 访问指令，并将目标数据返回到存储器控制器。 在本发明的实施例中，系统存储器的级联方式改变为树形拓扑形式。 这避免了协议转换问题，减少了内存访问时间，并提高了内存访问效率。

公开(公告)号：EP1751762B1

公开(公告)日：2010-04-21

申请号：EP05742846.8

申请日：2005-04-28

Applicant: Freescale Semiconductor, Inc.

Inventor： PELLEY, Perry, H.

IPC: G11C11/406

CPC classification number: G11C11/40607 ,  G11C7/1075 ,  G11C11/406 ,  G11C11/40618

公开(公告)号：EP3306615A1

公开(公告)日：2018-04-11

申请号：EP17195234.4

申请日：2017-10-06

Applicant: Kilopass Technology, Inc.

Inventor： Ong, Adrian E. ,  Cheng, Charles

IPC: G11C11/39 ,  G11C16/34 ,  G11C11/406

CPC classification number: G11C11/39 ,  G11C11/40607 ,  G11C15/04 ,  G11C16/3418

Abstract: Methods and systems are described herein for determining if bit cell read or write rates require a refresh of the accessed or neighboring bit cells. The refresh of VLT memory bit cells that undergo a high frequency of page address read operations and write operations helps to maintain integrity of data stored in the VLT memory bit cells. The methods and systems determine, during each RAS cycle, if a rate of Page Address read operations or write operations exceeds a maximum rate across an interval, and conditionally cause a refresh operation if the rate exceeds the maximum rate. The methods and systems output a write back signal to cause a refresh of the associated VLT memory bit cells to prevent corruption of data stored in the associated VLT memory bit cells.

Abstract translation: 本文描述了用于确定位单元读取或写入速率是否需要刷新访问的或相邻的位单元的方法和系统。 经历页面地址读取操作和写入操作的高频率的VLT存储器位单元的刷新有助于维持存储在VLT存储器位单元中的数据的完整性。 在每个RAS周期期间，这些方法和系统确定页面地址读取操作或写入操作的速率是否超过间隔内的最大速率，并且如果速率超过最大速率则有条件地引起刷新操作。 该方法和系统输出回写信号以引起关联的VLT存储器位单元的刷新，以防止存储在关联的VLT存储器位单元中的数据的损坏。

公开(公告)号：EP2985699A1

公开(公告)日：2016-02-17

申请号：EP14788484.5

申请日：2014-04-10

Applicant: Huawei Technologies Co., Ltd.

Inventor： RUAN, Yuan ,  CHEN, Mingyu

IPC: G06F12/08

CPC classification number: G11C11/40607 ,  G06F12/02 ,  G06F13/1673 ,  G11C7/1063 ,  G11C7/1072

Abstract: Embodiments of the present invention provide a memory access method and a memory system. A memory controller sends a memory access instruction, a lower-order address signal, a first chip select signal, and a first higher-order address signal to a first level buffer chip, delays a second higher-order address signal to obtain a delayed address signal, and sends the delayed address signal to a second level buffer chip. The first level buffer chip gates a target second level buffer chip according to a preset mapping relationship, the first chip select signal, and the first higher-order address signal, and sends the memory access instruction and the lower-order address signal to the target second level buffer chip. The target second level buffer chip determines a target memory module according to the delayed address signal and a second chip select signal, determines a target memory chip according to the lower-order address signal, acquires target data from the target memory chip according to the memory access instruction, and returns the target data to the memory controller. In the embodiments of the present invention, a cascading manner of a system memory is changed to a tree-like topological form. This avoids a protocol conversion problem, reduces the memory access time, and improves the memory access efficiency.

Abstract translation: 本发明的实施例提供了一种存储器访问方法和存储器系统。 存储器控制器向第一级缓冲器芯片发送存储器访问指令，低位地址信号，第一芯片选择信号和第一高位地址信号，延迟第二高位地址信号以获得延迟地址 信号，并将延迟的地址信号发送到第二级缓冲器芯片。 第一级缓冲芯片根据预设的映射关系，第一芯片选择信号和第一高位地址信号选通目标第二级缓存芯片，并将存储器访问指令和低位地址信号发送给目标 二级缓冲芯片。 目标第二级缓冲芯片根据延迟地址信号和第二芯片选择信号确定目标存储器模块，根据低位地址信号确定目标存储器芯片，根据存储器从目标存储器芯片获取目标数据 访问指令，并将目标数据返回给内存控制器。 在本发明实施例中，将系统存储器的级联方式改变为树状拓扑形式。 这避免了协议转换问题，减少了存储器访问时间，并提高了存储器访问效率。

公开(公告)号：EP2815321A4

公开(公告)日：2015-02-25

申请号：EP13749682

申请日：2013-01-08

Applicant: IBM

Inventor： DODSON JOHN STEVEN ,  STUECHELI JEFFREY ,  BRITTAIN MARK ANDREW ,  POWELL STEPHEN ,  RETTER ERIC EUGENE

IPC: G06F12/00 ,  G06F13/16 ,  G11C11/406

CPC classification number: G11C11/40607 ,  G06F13/1626 ,  G06F13/1689

公开(公告)号：EP2207184A1

公开(公告)日：2010-07-14

申请号：EP10155879.9

申请日：2005-04-28

Applicant: Freescale Semiconductor, Inc.

Inventor： Pelley, Perry, H

IPC: G11C11/406

CPC classification number: G11C11/40607 ,  G11C7/1075 ,  G11C11/406 ,  G11C11/40618

Abstract: Amcthod for refreshing a memory (10) having a plurality of refreshable memory cells organized in a plurality of memory banks (14, 16, 18, 20). The method comprises accessing the memory (10) for a burst operation; and detecting an access to one of the plurality of memory banks (14, 16, 18, 20) during the burst operation. The method further comprises refreshing memory cells of a bank of the plurality of memory banks (14, 16, 18, 20) that is not being accessed during the burst operation in response to the burst operation.

Abstract translation: 用于刷新具有组织在多个存储体（14,16,18,20）中的多个可刷新存储器单元的存储器（10）的方法。 该方法包括访问用于突发操作的存储器（10） 以及在所述突发操作期间检测对所述多个存储器组（14,16,18,20）中的一个的访问。 该方法还包括刷新多个存储器组（14,16,18,20）的存储单元，该存储器单元响应于突发操作而在突发操作期间未被访问。

公开(公告)号：EP1564751A4

公开(公告)日：2007-07-18

申请号：EP03769944

申请日：2003-10-29

Applicant: SONY CORP

Inventor： SHIMOYAMA TAKESHI

IPC: G11C11/401 ,  G11C11/407 ,  G11C7/06 ,  G11C7/10 ,  G11C11/403 ,  G11C11/4091

CPC classification number: G11C11/40607 ,  G06F2212/3042 ,  G11C7/065 ,  G11C7/1072 ,  G11C11/4091 ,  G11C2207/2245

Abstract: A synchronous information storage device that controls the operation timing using a synchronous clock and exhibits improved performance through highly efficient operation processing and reduced power consumption of feature of DRAMs. The information storage device comprises a plurality of memory cells in which data is stored by storing electrical charges; and an amplifier that amplifies the charges of the memory cells, wherein a synchronous clock is used to time the input/output of the data. This information storage device performs two operations, that is, a charge extraction operation that extracts electrical charges transferred from the memory cells to the amplifier or a charge storing operation that stores charges from the amplifier into the memory cells and an input/output operation of the amplifier from/to a unit external to the information storage device, using the single clock of the synchronous clock for the timing.

公开(公告)号：EP1751762A2

公开(公告)日：2007-02-14

申请号：EP05742846.8

申请日：2005-04-28

Applicant: Freescale Semiconductor, Inc.

Inventor： PELLEY, Perry, H.

IPC: G11C7/00

CPC classification number: G11C11/40607 ,  G11C7/1075 ,  G11C11/406 ,  G11C11/40618

Abstract: A memory (10) has a plurality of memory cells, a serial address port (47) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is stored in the memory array (14) by interleaving in multiple sub-arrays (15, 17). During a hidden refresh mode of operation, one sub-array (15) is accessed while another sub-array (17) is refreshed. Two or more of the memories (10) may be chained together to provide a high speed low power memory system.

公开(公告)号：EP3279899A4

公开(公告)日：2018-03-28

申请号：EP15891059

申请日：2015-05-04

Applicant: HUAWEI TECH CO LTD

Inventor： XIAO SHIHAI ,  HUANG YONGBING ,  HE RUI

IPC: G11C11/406 ,  G11C11/403

CPC classification number: G11C29/783 ,  G11C11/403 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4091

Abstract: A DRAM refresh method, apparatus, and system are provided. A to-be-refreshed area in a refresh block is specified in a refresh instruction, so as to refresh a specified location of a DRAM storage array. The method includes: receiving, by a DRAM refresh apparatus, a refresh instruction from a memory controller, where the refresh instruction includes an identifier of a to-be-refreshed block and refresh information used to indicate a to-be-refreshed area, and the refresh instruction is used to instruct the DRAM refresh apparatus to refresh the to-be-refreshed area in the to-be-refreshed block (S902); generating, by the DRAM refresh apparatus, addresses of to-be-refreshed bank rows in the to-be-refreshed block according to the identifier and the refresh information (S904); and refreshing, by the DRAM refresh apparatus, locations corresponding to the addresses of the bank rows in the to-be-refreshed block (S906). In this way, a DRAM refresh time is shortened, refresh power consumption is reduced, a refresh operation is more flexible, and system resource consumption is reduced while data integrity is ensured.

公开(公告)号：EP2985699B1

公开(公告)日：2017-09-06

申请号：EP14788484.5

申请日：2014-04-10

Applicant: Huawei Technologies Co., Ltd.

Inventor： RUAN, Yuan ,  CHEN, Mingyu

IPC: G06F12/02 ,  G11C7/10 ,  G11C11/406 ,  G06F13/16 ,  G06F12/08

CPC classification number: G11C11/40607 ,  G06F12/02 ,  G06F13/1673 ,  G11C7/1063 ,  G11C7/1072

Abstract: Embodiments of the present invention provide a memory access method and a memory system. A memory controller sends a memory access instruction, a lower-order address signal, a first chip select signal, and a first higher-order address signal to a first level buffer chip, delays a second higher-order address signal to obtain a delayed address signal, and sends the delayed address signal to a second level buffer chip. The first level buffer chip gates a target second level buffer chip according to a preset mapping relationship, the first chip select signal, and the first higher-order address signal, and sends the memory access instruction and the lower-order address signal to the target second level buffer chip. The target second level buffer chip determines a target memory module according to the delayed address signal and a second chip select signal, determines a target memory chip according to the lower-order address signal, acquires target data from the target memory chip according to the memory access instruction, and returns the target data to the memory controller. In the embodiments of the present invention, a cascading manner of a system memory is changed to a tree-like topological form. This avoids a protocol conversion problem, reduces the memory access time, and improves the memory access efficiency.